MEMORY CONTROLLER FOR RECEIVING DIFFERENTIAL DATA STROBE SIGNALS AND APPLICATION PROCESSOR HAVING THE MEMORY CONTROLLER

• US 20180165023A1
• Filed: 02/15/2017
• Published: 06/14/2018
• Est. Priority Date: 12/08/2016
• Status: Inactive Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: OH, Ji-hun, PARK, Sang-hune, CHOI, Jin-ho, CHOI, Jong-ryun, KIM, Dae-ro
• Granted Patent: US 10,572,406 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller for receiving a differential data strobe signal and an application processor having the memory controller are disclosed. The memory controller includes a strobe signal receiver configured to receive first and second strobe signals from a memory device as differential data strobe signal and output a first detection signal based on a level of each of the first and second strobe signals, a comparator configured to receive the second strobe signal and a reference voltage and compare a level of the second strobe signal with a level of the reference voltage to output a second detection signal, and a gate signal generator configured to generate a gate signal masking a portion of a period corresponding to the differential data strobe signal using the first detection signal and the second detection signal.

Claims

1. A memory controller comprising:

a strobe signal receiver configured to receive first and second strobe signals from a memory device as differential data strobe signals and output a first detection signal based on a level of each of the first and second strobe signals;

a comparator configured to receive the second strobe signal and a reference voltage and compare a level of the second strobe signal with a level of the reference voltage to output a second detection signal based on a comparison result; and

a gate signal generator configured to generate a gate signal masking a portion of a period corresponding to the differential data strobe signals based on the first detection signal and the second detection signal,

wherein the gate signal generator includes a counter configured to count a toggle of the second detection signal and the gate signal generator is configured to generate the gate signal based on the counting result from the counter.

2. The memory controller of claim 1, further comprising a clean strobe signal generator configured to receive the gate signal and the first detection signal from the strobe signal receiver and generate a clean strobe signal used to latch data provided from the memory device.

3. The memory controller of claim 2, further comprising one or more flip-flops configured to latch the data provided from the memory device in response to the clean strobe signal.

4. The memory controller of claim 1, wherein the memory controller is configured to output sequentially first and second read commands,

wherein an idle period and a preamble period exist between data readout periods corresponding to the first and second read commands, and

wherein the differential data strobe signal is masked by the gate signal in at least a portion of the idle period and the preamble period.

5. The memory controller of claim 4, wherein the gate signal generator is configured to generate a first internal signal activated in response to the second detection signal at a start time of the preamble period and a second internal signal activated in response to the first detection signal in the preamble period,

wherein each of the first and second internal signals comprises an active period corresponding to a readout burst length, and

wherein the gate signal is generated based on at least one of the first and second internal signals.

6. The memory controller of claim 5, wherein the gate signal generator is configured to further generate a third internal signal by performing an OR operation on the first internal signal and the second internal signal and to selectively output the second internal signal or the third internal signal as the gate signal based on the existence of toggling of the differential data strobe signals in the preamble period.

7. The memory controller of claim 1, wherein the memory controller is configured to consecutively output first and second read commands to the memory device, further comprising:

an interval detection circuit configured to detect an interval between the first and second read commands and output an interval detection result; and

a storing circuit configured to store the interval detection result.

8. The memory controller of claim 7, wherein the gate signal generator is configured to generate the gate signal further based on the interval detection result, and

wherein the gate signal is activated or inactivated based on the interval detection result checked when the counter counts a first value.

9. The memory controller of claim 8, wherein the gate signal is inactivated in response to counting of the first value in a case where at least one of an idle period and a preamble period is determined to exist before a data readout period corresponding to the second read command based on the interval detection result, and

wherein the gate signal is maintained in an active state in response to counting of the first value in a case where the idle period and the preamble period are determined not to exist based on the interval detection result.

10. The memory controller of claim 7, wherein the storing circuit is configured to store the interval detection result in response to a write enable signal from the interval detection circuit and provide the interval detection result to the gate signal generator in response to a readout enable signal from the gate signal generator.

11. A memory controller comprising:

a strobe signal receiver configured to receive first and second strobe signals as differential data strobe signals and output a first detection signal based on a level of each of the first and second strobe signals;

an interval detection circuit configured to detect an interval between read commands provided to a memory device and output an interval detection result; and

a gate signal generator configured to generate a gate signal masking a portion of a period corresponding to the differential data strobe signal, based on the first detection signal and the interval detection result.

12. The memory controller of claim 11, wherein the memory controller is configured to output sequentially first and second read commands,

wherein an idle period and a preamble period exist between data readout periods according to the interval between the first and second read commands, and

wherein the gate signal generator is configured to generate the gate signal having an inactive period to mask at least a portion of the idle period and the preamble period based on the interval detection result.

13. The memory controller of claim 11, wherein the gate signal generator is configured to generate an internal signal activated in synchronization with the first detection signal and inactivated based on the interval detection result, and

wherein the gate signal generator is configured to generate the gate signal based on the internal signal.

14. The memory controller of claim 11, further comprising a comparator configured to compare a level of the second strobe signal with a level of a reference voltage to output a second detection signal,

wherein the gate signal generator is configured to generate the gate signal based on the second detection signal.

15. The memory controller of claim 14, wherein when an idle period and a preamble period exist between data readout periods according to the interval between the read commands, the gate signal generator is further configured to generate a glitch control signal activated in at least a portion of the idle period to mask a glitch occurring in the second detection signal during the idle period and generate the gate signal based on the glitch control signal.

16. A memory system comprising:

a memory device; and

a memory controller connected to the memory device and configured to generate read commands and write commands, receive data from the memory device, and transmit data to the memory device,

wherein one of the memory controller and the memory device comprising;

a strobe signal receiver configured to output a first detection signal based on first and second strobe signals externally received;

a comparator configured to compare one of the first and second strobe signals with a reference voltage and output a second detection signal based on the comparison result;

a gate signal generator configured to generate a gate signal to transfer the first detection signal during an active state of the gate signal or to block the first detection signal during an inactive state of the gate signal, based on the first and second detection signals and an interval between consecutively generated read commands or write commands; and

a strobe signal generator configured to output a data strobe signal based on the first detection signal and the gate signal,

wherein the memory controller is configured to receive/transmit data from/to the memory device in synchronization with the data strobe signal.

17. The memory system of claim 16, wherein the gate signal generator includes a counter configured to count a rising edge or a falling edge of one of the first and second detection signals, and

wherein the counter is configured to perform a count operation based on the interval between consecutively generated read commands or write commands.

18. The memory system of claim 16, wherein when the interval between consecutively generated the read commands or the write commands is equal to or less than a first value, the gate signal generator is configured to generate the gate signal having only active state to transfer the first detection signal during a period corresponding to the interval of the first value.

19. The memory system of claim 16, wherein the gate signal generator is configured to further generate a glitch control signal to remove a glitch occurred in the second detection signal during an idle period between data readout periods corresponding to the consecutive read commands.

20. The memory system of claim 16, wherein a first input terminal of the strobe signal receiver is connected to a first on-die termination circuit and a second input terminal of the strobe signal receiver is connected to a second on-die termination circuit.