MIGRATION BETWEEN CPU CORES

• US 20180165120A1
• Filed: 02/07/2018
• Published: 06/14/2018
• Est. Priority Date: 08/26/2015
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: NetApp, Inc.
• Inventors: Prosch, Kent, Weber, Matthew, Banerjee, Arindam, McDavitt, Ben
• Granted Patent: US 10,459,759 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 2209/482 Application
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

Methods, non-transitory machine-readable media, and computing devices for transitioning tasks and interrupt service routines are provided. An example method includes processing, by a plurality of processor cores of a storage controller, tasks and interrupt service routines. A performance statistic is determined corresponding to the plurality of processor cores. Based on detecting that the performance statistic passes a threshold, a number of the plurality of processor cores that are assigned to the tasks and the interrupt service routines are reduced.

Claims

1. A method comprising:

processing, by a plurality of processor cores of a storage controller, one or more tasks and one or more interrupt service routines;

determining a performance statistic corresponding to the plurality of processor cores; and

responsive to detecting that the performance statistic passes a threshold, reducing a number of the plurality of processor cores that are assigned to process the one or more tasks and the one or more interrupt service routines.

2. The method of claim 1, wherein the performance statistic includes an operations request rate.

3. The method of claim 1, wherein the detecting that the performance statistic passes the threshold comprises:

detecting that an operations response rate corresponding to the plurality of processor cores is below the threshold.

4. The method of claim 1, wherein the reducing of the number of the plurality of processor cores includes transitioning from a multi-core configuration to a single-core configuration.

5. The method of claim 1, wherein the reducing of the number of the plurality of processor cores includes migrating a task of the one or more of the tasks and an interrupt service routine of the one or more interrupt service routines from a source processor core of the plurality of cores to a target processor core of the plurality of cores.

6. The method of claim 1, wherein the migrating of the task comprises:

identifying, based on a mapping, that the target core corresponds to the task;

responsive to the identifying, blocking the source core from processing the task; and

assigning the target core to process the task.

7. The method of claim 1, wherein the migrating of the interrupt service routine comprises:

identifying, based on a mapping, that the target core corresponds to the interrupt service routine;

responsive to the identifying, disabling an interrupt corresponding to the interrupt service routine;

assigning the interrupt to the target core; and

after assigning the interrupt to the target core, enabling the interrupt.

8. A non-transitory machine-readable medium having stored thereon instructions for performing a method comprising machine executable code that when executed by at least one machine, causes the machine to:

process, by a plurality of processor cores, one or more tasks and one or more interrupt service routines;

determine an operations request rate corresponding to the plurality of processor cores; and

responsive to detecting that the operations request rate is below a threshold, reduce a number of the plurality of processor cores that are assigned to process the one or more tasks and handle interrupts corresponding to the one or more interrupt service routines.

9. The non-transitory machine-readable medium of claim 8, wherein the reducing of the number of the plurality of processor cores includes transitioning from a multi-core configuration to a single-core configuration.

10. The non-transitory machine-readable medium of claim 8, wherein the reducing of the number of the plurality of processor cores includes migrating a task of the one or more of the tasks from a source processor core of the plurality of cores to a target processor core of the plurality of cores.

11. The non-transitory machine-readable medium of claim 10, wherein the migrating of the task comprises:

identifying, based on a mapping, that the target core corresponds to the task;

responsive to the identifying, blocking the source core from processing the task; and

assigning the target core to process the task

12. The non-transitory machine-readable medium of claim 8, wherein the reducing of the number of the plurality of processor cores includes migrating an interrupt service routine of the one or more interrupt service routines from a source processor core of the plurality of cores to a target processor core of the plurality of cores.

13. The non-transitory machine-readable medium of claim 8, wherein the migrating of the interrupt service routine comprises:

identifying, based on a mapping, that the target core corresponds to the interrupt service routine;

responsive to the identifying, disabling an interrupt corresponding to the interrupt service routine;

assigning the interrupt to the target core; and

after assigning the interrupt to the target core, enabling the interrupt.

14. A computing device comprising:

a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of transitioning tasks and interrupts from a multi-core configuration to a single-core configuration; and

a processor coupled to the memory, the processor configured to execute the machine executable code to cause the processor to;

process, by a plurality of cores, one or more tasks and one or more interrupt service routines;

determine a performance statistic corresponding to the plurality of cores; and

responsive to detecting that the performance statistic passes a threshold, reduce an amount of the plurality of cores that are assigned to process the one or more tasks and handle interrupts corresponding to the one or more interrupt service routines.

15. The computing device of claim 15, wherein the performance statistic includes an operations request rate.

16. The computing device of claim 15, wherein the detecting that the performance statistic passes the threshold comprises:

detecting that an operations response rate corresponding to the plurality of processor cores is below the threshold.

17. The computing device of claim 15, wherein the reducing of the amount of the plurality of processor cores includes migrating a task of the one or more of the tasks from a source processor core of the plurality of cores to a target processor core of the plurality of cores.

18. The computing device of claim 17, wherein the migrating of the task comprises:

identifying, based on a mapping, that the target core corresponds to the task;

responsive to the identifying, blocking the source core from processing the task; and

assigning the target core to process the task

19. The computing device of claim 15, wherein the reducing of the amount of the plurality of processor cores includes migrating an interrupt service routine of the one or more interrupt service routines from a source processor core of the plurality of cores to a target processor core of the plurality of cores.

20. The computing device of claim 19, wherein the migrating of the interrupt service routine comprises:

identifying, based on a mapping, that the target core corresponds to the interrupt service routine;

responsive to the identifying, disabling an interrupt corresponding to the interrupt service routine;

assigning the interrupt to the target core; and

after assigning the interrupt to the target core, enabling the interrupt.