Programmable Memory Prefetcher

• US 20180165204A1
• Filed: 12/12/2016
• Published: 06/14/2018
• Est. Priority Date: 12/12/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Venkatesh, Ganesh, Wilkerson, Christopher B., Pugsley, Seth H., Marr, Deborah T.
• Granted Patent: US 10,452,551 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions

Abstract

A processor may include a programmable hardware prefetch engine and a prefetch engine control register. The processor may include circuitry to receive, during execution of an application, a first instruction for configuring the prefetch engine for prefetching multiple cache lines to be accessed in the future, at predictable locations, by the application; to store, in the prefetch engine control register, dependent on information in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched; to receive a second instruction for prefetching a single cache line whose location is identified in the second instruction; and to initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the prefetch engine, to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register.

Claims

1. A processor, comprising:

a programmable hardware prefetch engine;

a prefetch engine control register;

circuitry to;

receive, during execution of an application on the processor, a first instruction executable to configure the programmable hardware prefetch engine for prefetching multiple cache lines to be accessed in the future, at locations addressable in a predictable pattern, by the application;

store, in the prefetch engine control register, dependent on information included in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched;

receive a second instruction executable to prefetch a single cache line whose location is identified by a parameter of the second instruction;

initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the programmable hardware prefetch engine, the prefetching to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register.

2. The processor of claim 1, wherein the first instruction comprises a write request that targets the prefetch engine control register.

3. The processor of claim 1, wherein:

the prefetch engine control register includes multiple entries, each of which includes an identifier of a respective operation to prefetch, by the programmable hardware prefetch engine, multiple cache lines;

the first instruction specifies an identifier of a given operation to prefetch, by the programmable hardware prefetch engine, multiple cache lines;

the processor further includes circuitry to;

store the data representing an amount of prefetching to be performed, the data representing a stride distance between consecutive ones of the multiple cache lines to be prefetched, and the identifier of the given operation in one of the entries in the prefetch engine control register.

4. The processor of claim 1, further comprising circuitry to:

store, in the prefetch engine control register, dependent on information included in the first instruction, data representing a number of execution cycles for which to wait between prefetching consecutives ones of the multiple cache lines.

5. The processor of claim 1, wherein the programmable hardware prefetch engine comprises circuitry to:

prefetch the multiple cache lines from a last-level cache to a mid-level cache in the processor.

6. The processor of claim 1, wherein the programmable hardware prefetch engine comprises a hardware state machine to prefetch the multiple cache lines asynchronously and in parallel with the execution of the application.

7. The processor of claim 1, further comprising circuitry to:

receive a third instruction executable to disable the prefetching of the multiple cache lines by the programmable hardware prefetch engine;

store, in the prefetch engine control register in response to receipt of the third instruction, data indicating that the programmable hardware prefetch engine is no longer enabled to perform the prefetching of the multiple cache lines.

8. A method comprising, in a processor:

receiving, during execution of an application on the processor, a first instruction for configuring a programmable hardware prefetch engine for prefetching multiple cache lines to be accessed in the future, at locations addressable in a predictable pattern, by the application;

storing, in a prefetch engine control register, dependent on information included in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched;

receiving a second instruction for prefetching a single cache line whose location is identified by a parameter of the second instruction;

initiating, in response to receiving the second instruction, prefetching of multiple cache lines by the programmable hardware prefetch engine, the prefetching to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register.

9. The method of claim 8, wherein:

the prefetch engine control register includes multiple entries, each of which includes an identifier of a respective operation to prefetch, by the programmable hardware prefetch engine, multiple cache lines;

the first instruction specifies an identifier of a given operation to prefetch, by the programmable hardware prefetch engine, multiple cache lines;

the method further includes;

storing the data representing an amount of prefetching to be performed, the data representing a stride distance between consecutive ones of the multiple cache lines to be prefetched, and the identifier of the given operation in one of the entries in the prefetch engine control register.

10. The method of claim 8, further comprising:

storing, in the prefetch engine control register, dependent on information included in the first instruction, data representing a number of execution cycles for which to wait between prefetching consecutives ones of the multiple cache lines.

11. The method of claim 8, further comprising:

prefetching the multiple cache lines from a last-level cache to a mid-level cache in the processor.

12. The method of claim 8, wherein:

the programmable hardware prefetch engine comprises a hardware state machine;

the method further comprises prefetching, by the hardware state machine, the multiple cache lines asynchronously and in parallel with the execution of the application.

13. The method of claim 8, further comprising:

receiving a third instruction for disabling the prefetching of the multiple cache lines by the programmable hardware prefetch engine;

storing, in the prefetch engine control register in response to receiving the third instruction, data indicating that the programmable hardware prefetch engine is no longer enabled to perform the prefetching of the multiple cache lines.

14. A system, comprising:

a processor, comprising;

a programmable hardware prefetch engine;

a prefetch engine control register;

a memory storing program instructions that when executed by the processor implement an application, the program instructions comprising;

a first instruction executable to configure the programmable hardware prefetch engine for prefetching multiple cache lines to be accessed in the future, at locations addressable in a predictable pattern, by the application;

a second instruction executable to prefetch a single cache line whose location is identified by a parameter of the first instruction;

wherein the system further includes circuitry to;

receive, during execution of the application, the first instruction;

store, in the prefetch engine control register, dependent on information included in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched;

receive the second instruction;

initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the programmable hardware prefetch engine, the prefetching to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register.

15. The system of claim 14, wherein the first instruction comprises a write request that targets the prefetch engine control register.

16. The system of claim 14, wherein:

the prefetch engine control register includes multiple entries, each of which includes an identifier of a respective operation to prefetch, by the programmable hardware prefetch engine, multiple cache lines;

the first instruction specifies an identifier of a given operation to prefetch, by the programmable hardware prefetch engine, multiple cache lines;

the system further includes circuitry to;

store the data representing an amount of prefetching to be performed, the data representing a stride distance between consecutive ones of the multiple cache lines to be prefetched, and the identifier of the given operation in one of the entries in the prefetch engine control register.

17. The system of claim 14, further comprising circuitry to:

store, in the prefetch engine control register, dependent on information included in the first instruction, data representing a number of execution cycles for which to wait between prefetching consecutives ones of the multiple cache lines.

18. The system of claim 14, wherein the programmable hardware prefetch engine comprises circuitry to:

prefetch the multiple cache lines from a last-level cache to a mid-level cache in the system.

19. The system of claim 14, wherein the programmable hardware prefetch engine comprises a hardware state machine to prefetch the multiple cache lines asynchronously and in parallel with the execution of the application.

20. The system of claim 14, wherein:

the program instructions further include a third instruction executable to disable the prefetching of the multiple cache lines by the programmable hardware prefetch engine;

the system further includes circuitry to;

store, in the prefetch engine control register in response to receipt of the first instruction, data indicating that the programmable hardware prefetch engine is enabled to perform the prefetching of the multiple cache lines;

receive the third instruction;

store, in the prefetch engine control register in response to receipt of the third instruction, data indicating that the programmable hardware prefetch engine is no longer enabled to perform the prefetching of the multiple cache lines.