Programmable Memory Prefetcher
First Claim
1. A processor, comprising:
- a programmable hardware prefetch engine;
a prefetch engine control register;
circuitry to;
receive, during execution of an application on the processor, a first instruction executable to configure the programmable hardware prefetch engine for prefetching multiple cache lines to be accessed in the future, at locations addressable in a predictable pattern, by the application;
store, in the prefetch engine control register, dependent on information included in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched;
receive a second instruction executable to prefetch a single cache line whose location is identified by a parameter of the second instruction;
initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the programmable hardware prefetch engine, the prefetching to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register.
1 Assignment
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Accused Products
Abstract
A processor may include a programmable hardware prefetch engine and a prefetch engine control register. The processor may include circuitry to receive, during execution of an application, a first instruction for configuring the prefetch engine for prefetching multiple cache lines to be accessed in the future, at predictable locations, by the application; to store, in the prefetch engine control register, dependent on information in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched; to receive a second instruction for prefetching a single cache line whose location is identified in the second instruction; and to initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the prefetch engine, to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register.
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Citations
20 Claims
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1. A processor, comprising:
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a programmable hardware prefetch engine; a prefetch engine control register; circuitry to; receive, during execution of an application on the processor, a first instruction executable to configure the programmable hardware prefetch engine for prefetching multiple cache lines to be accessed in the future, at locations addressable in a predictable pattern, by the application; store, in the prefetch engine control register, dependent on information included in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched; receive a second instruction executable to prefetch a single cache line whose location is identified by a parameter of the second instruction; initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the programmable hardware prefetch engine, the prefetching to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising, in a processor:
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receiving, during execution of an application on the processor, a first instruction for configuring a programmable hardware prefetch engine for prefetching multiple cache lines to be accessed in the future, at locations addressable in a predictable pattern, by the application; storing, in a prefetch engine control register, dependent on information included in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched; receiving a second instruction for prefetching a single cache line whose location is identified by a parameter of the second instruction; initiating, in response to receiving the second instruction, prefetching of multiple cache lines by the programmable hardware prefetch engine, the prefetching to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A system, comprising:
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a processor, comprising; a programmable hardware prefetch engine; a prefetch engine control register; a memory storing program instructions that when executed by the processor implement an application, the program instructions comprising; a first instruction executable to configure the programmable hardware prefetch engine for prefetching multiple cache lines to be accessed in the future, at locations addressable in a predictable pattern, by the application; a second instruction executable to prefetch a single cache line whose location is identified by a parameter of the first instruction; wherein the system further includes circuitry to; receive, during execution of the application, the first instruction; store, in the prefetch engine control register, dependent on information included in the first instruction, data representing an amount of prefetching to be performed and data representing a stride distance between consecutive cache lines to be prefetched; receive the second instruction; initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the programmable hardware prefetch engine, the prefetching to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification