MEMORY MANAGEMENT

• US 20180165218A1
• Filed: 12/05/2017
• Published: 06/14/2018
• Est. Priority Date: 12/09/2016
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Parker, Jason, Swaine, Andrew Brookfield
• Granted Patent: US 10,733,111 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1416 by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights G06F12/1458 takes precedence
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/651 Multi-level translation tables
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB
• CPC Class Codes: G06F 2212/684 TLB miss handling

Abstract

Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.

Claims

1. Apparatus comprising:

input circuitry to receive a translation request defining an input memory address within an input memory address space; and

address translation circuitry comprising;

permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and

output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.

2. Apparatus according to claim 1, in which the permission circuitry is configured to store permission data for a set of contiguous regions of the input memory address space, such that each possible input memory address of the input memory address space is within a respective one of the regions.

3. Apparatus according to claim 1, comprising:

second translation circuitry to generate a translation of an input memory address to an output memory address;

in which, when the permission circuitry does not indicate that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide a translation generated by the second translation circuitry.

4. Apparatus according to claim 3, in which the second translation circuitry is configured to perform address translation with reference to the address translation tables.

5. Apparatus according to claim 4, in which the second translation circuitry comprises:

a translation lookaside buffer to store translations in respect of a subset of input memory addresses in the input memory address space; and

circuitry to access the address translation tables to obtain a translation of an input memory address for which a translation is not stored by the translation lookaside buffer.

6. Apparatus according to claim 5, in which the address translation tables comprise a hierarchy of two or more page table levels, in which a page table in a higher level indicates, for a block of input memory addresses having a block size associated with that page table level, either:

a respective one of a set or two or more page tables in a next level;

or

an address mapping applicable to that block of input memory addresses.

7. Apparatus according to claim 6, in which:

the regions have a region size equal to the block size associated with one of the page table levels other than a lowest page table level in the hierarchy of page table levels.

8. Apparatus according to claim 3, in which:

when the second translation circuitry generates a translation of an input memory address to an output memory address, the permission circuitry is configured to store permission data for that region of the input memory address space dependent upon the generated translation provided that the translation meets a set of criteria comprising;

the translation is valid across the whole of one of the regions of the input memory address space; and

the translation is such that output memory addresses are related by the predetermined function to input memory addresses within the region.

9. Apparatus according to claim 8, in which the set of criteria comprises:

the translation grants access permissions which correspond to access permissions which can be stored by the permission circuitry.

10. Apparatus according to claim 1, comprising:

a supervising processor to control storage of the address translation tables and to write permission data to the permission circuitry in dependence upon the address translation tables.

11. Apparatus according to claim 1, in which the input memory address is one of a physical address and a virtual memory address, and the output memory address is a physical memory address.

12. Apparatus according to claim 1, in which the predetermined function is such that the output memory address is equal to the input memory address.

13. Apparatus according to claim 1, in which:

the permission circuitry is configured to store data identifying the predetermined function.

14. Data processing apparatus comprising:

one or more memories accessible according to physical memory addresses;

one or more data processing nodes to generate translation requests from a virtual memory address generated by that data processing node to a physical memory address to access the one or more memories; and

address translation apparatus comprising apparatus according to claim 1 to translate a virtual address from a data processing node to a physical address to access the one or more memories.

15. Data processing apparatus comprising:

one or more memories accessible according to physical memory addresses;

one or more data processing nodes to generate translation requests from a virtual memory address generated by that data processing node to a physical memory address to access the one or more memories; and

address translation apparatus comprising apparatus according to claim 12 to translate a virtual address from a data processing node to a physical address to access the one or more memories.

16. Data processing apparatus according to claim 14 in which:

the one or more data processing nodes have respective associated cache storage;

the data processing apparatus comprises coherency control circuitry; and

the one or more memories and the cache storage are configured to operate under the control of the coherency control circuitry to store one or more copies of data accessible by each of the data processing nodes, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements.

17. Data processing apparatus according to claim 16, in which:

the coherency control circuitry is configured to communicate with the cache storage in respect of data held by the cache storage using a physical memory address by which that data is stored in the one or more memories.

18. Data processing apparatus according to claim 17, in which the address translation apparatus is configured to allow a cache allocating read operation from the one or more memories and a cachable coherent write to the one or more memories.

19. A method comprising:

receiving a translation request defining an input memory address within an input memory address space;

detecting whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and

providing an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.