Method and Computer Program for Determining a Placement of at least one Circuit for a Reconfigurable Logic Device
First Claim
1. A method for determining a placement of at least one circuit for a reconfigurable logic device, the method comprising:
- obtaining information related to the at least one circuit, wherein the at least one circuit comprises a plurality of blocks and a plurality of connections between the plurality of blocks, and wherein the plurality of blocks comprise a plurality of logic blocks and a plurality of input/output blocks;
calculating a circuit graph based on the information related to the at least one circuit, wherein the circuit graph comprises a plurality of nodes and a plurality of edges, wherein the plurality of nodes represent at least a subset of the plurality of blocks of the at least one circuit and wherein the plurality of edges represent at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit;
determining a force-directed layout of the circuit graph, wherein the force-directed layout is based on attractive forces based on the plurality of connections between the plurality of blocks and based on repulsive forces between the plurality of blocks; and
determining a placement of the plurality of logic blocks onto a plurality of available logic cells of the reconfigurable logic device based on the force-directed layout of the circuit graphdetermining a placement of the plurality of input/output blocks onto a plurality of available input/output cells, wherein the determining of the placement of the plurality of input/output blocks is based on the force-directed layout of the circuit graph and based on the placement of the plurality of logic blocks.
1 Assignment
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Accused Products
Abstract
Embodiments relate to a method and computer program for determining a placement of at least one circuit for a reconfigurable logic device. The method comprises obtaining (110) information related to the at least one circuit. The at least one circuit comprises a plurality of blocks and a plurality of connections between the plurality of blocks. The plurality of blocks comprise a plurality of logic blocks. The method further comprises calculating (120) a circuit graph based on the information related to the at least one circuit. The circuit graph comprises a plurality of nodes and a plurality of edges. The plurality of nodes represent at least a subset of the plurality of blocks of the at least one circuit and wherein the plurality of edges represent at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit. The method further comprises determining (130) a force-directed layout of the circuit graph. The force-directed layout is based on attractive forces based on the plurality of connections between the plurality of blocks and based on repulsive forces between the plurality of blocks. The method further comprises determining (140) a placement of the plurality of logic blocks onto a plurality of available logic cells of the reconfigurable logic device based on the force-directed layout of the circuit graph.
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Citations
14 Claims
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1. A method for determining a placement of at least one circuit for a reconfigurable logic device, the method comprising:
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obtaining information related to the at least one circuit, wherein the at least one circuit comprises a plurality of blocks and a plurality of connections between the plurality of blocks, and wherein the plurality of blocks comprise a plurality of logic blocks and a plurality of input/output blocks; calculating a circuit graph based on the information related to the at least one circuit, wherein the circuit graph comprises a plurality of nodes and a plurality of edges, wherein the plurality of nodes represent at least a subset of the plurality of blocks of the at least one circuit and wherein the plurality of edges represent at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit; determining a force-directed layout of the circuit graph, wherein the force-directed layout is based on attractive forces based on the plurality of connections between the plurality of blocks and based on repulsive forces between the plurality of blocks; and determining a placement of the plurality of logic blocks onto a plurality of available logic cells of the reconfigurable logic device based on the force-directed layout of the circuit graph determining a placement of the plurality of input/output blocks onto a plurality of available input/output cells, wherein the determining of the placement of the plurality of input/output blocks is based on the force-directed layout of the circuit graph and based on the placement of the plurality of logic blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A computer program having a program code for performing a method comprising:
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obtaining information related to the at least one circuit, wherein the at least one circuit comprises a plurality of blocks and a plurality of connections between the plurality of blocks, and wherein the plurality of blocks comprise a plurality of logic blocks and a plurality of input/output blocks; calculating a circuit graph based on the information related to the at least one circuit, wherein the circuit graph comprises a plurality of nodes and a plurality of edges, wherein the plurality of nodes represent at least a subset of the plurality of blocks of the at least one circuit and wherein the plurality of edges represent at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit; determining a force-directed layout of the circuit graph, wherein the force-directed layout is based on attractive forces based on the plurality of connections between the plurality of blocks and based on repulsive forces between the plurality of blocks; and determining a placement of the plurality of logic blocks onto a plurality of available logic cells of the reconfigurable logic device based on the force-directed layout of the circuit graph determining a placement of the plurality of input/output blocks onto a plurality of available input/output cells, wherein the determining of the placement of the plurality of input/output blocks is based on the force-directed layout of the circuit graph and based on the placement of the plurality of logic blocks.
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Specification