Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making

• US 20180166446A1
• Filed: 02/08/2018
• Published: 06/14/2018
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 10,056,387 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1-54. -54. (canceled)

55. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector;

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors;

wherein said transistor is usable to access said memory cell;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and

a control circuit configured to provide electrical signals to said first and second collectors to maintain the states of said memory cells without interrupting access to said memory cells.

56. The integrated circuit of claim 55, wherein said number of said at least one contact is less than said number of said semiconductor memory cells.

57. The integrated circuit of claim 55, wherein said semiconductor memory cells are connected in series.

58. The integrated circuit of claim 55, wherein said semiconductor memory cells are connected in parallel.

59. The integrated circuit of claim 55, wherein said integrated circuit is fabricated on a bulk silicon substrate.

60. The integrated circuit of claim 55, wherein said link or string of semiconductor memory cells is formed in a fin structure.

61. The integrated circuit of claim 55, wherein said number of said at least one contact is two.

62. The integrated circuit of claim 55, wherein said gate is insulated from said floating body region.

63. The integrated circuit of claim 55, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

64. The integrated circuit of claim 63, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.

65. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector,

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell;

wherein said transistor is usable to access said memory cell;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string;

wherein at least one of said at least one control line is connected to a read circuitry;

wherein states of said memory cells are maintained upon repeated read operations; and

a control circuit configured to provide electrical signals to said first and second collectors to maintain the states of said memory cells without interrupting access to said memory cells.

66. The integrated circuit of claim 65, wherein said number of said at least one contact is less than said number of said semiconductor memory cells.

67. The integrated circuit of claim 65, wherein said semiconductor memory cells are connected in series.

68. The integrated circuit of claim 65, wherein said semiconductor memory cells are connected in parallel.

69. The integrated circuit of claim 65, wherein said integrated circuit is fabricated on a bulk silicon substrate.

70. The integrated circuit of claim 65, wherein said link or string of semiconductor memory cells is formed in a fin structure.

71. The integrated circuit of claim 65, wherein said number of said at least one contact is two.

72. The integrated circuit of claim 65, wherein said gate is insulated from said floating body region.

73. The integrated circuit of claim 65, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

74. The integrated circuit of claim 73, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.