Method of Forming Internal Spacer for Nanowires

• US 20180166534A1
• Filed: 11/27/2017
• Published: 06/14/2018
• Est. Priority Date: 12/09/2016
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Tao, Zheng, Chan, Boon Teik, Chew, Soon Aik
• Granted Patent: US 10,153,341 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

Claims

1. A method of forming a semiconductor device comprising horizontal nanowires, the method comprising:

providing a semiconductor structure comprising at least one fin, the at least one fin comprising a stack of layers of a sacrificial material alternated with layers of a nanowire material, the semiconductor structure comprising a dummy gate partly covering the stack of layers of the at least one fin;

at least partly removing the sacrificial material, in between the layers of the nanowire material, next to the dummy gate thereby forming a void;

providing spacer material within the void thereby forming an internal spacer;

removing the dummy gate; and

selectively removing the sacrificial material in a part of the at least one fin which was covered by the dummy gate, thereby releasing nanowires,

wherein the sacrificial material, in between the layers of the nanowire material, next to the dummy gate is removed and the internal spacer is provided before removing the dummy gate and the sacrificial material so as to release the nanowires.

2. The method according to claim 1, wherein the semiconductor structure further comprises a dummy gate spacer next to the dummy gate, and an inter-level dielectric (ILD) next to the dummy gate spacer such that the dummy gate spacer is in between the dummy gate and the ILD, the method further comprising:

before at least partly removing the sacrificial material next to the dummy gate, removing the dummy gate spacer thereby forming a trench,

wherein the at least partly removing the sacrificial material is started from an opening which is formed by the trench,

wherein providing the spacer material additionally comprises providing spacer material in the trench thereby forming the internal spacer next to the dummy gate.

3. The method according to claim 1, further comprising:

depositing gate dielectric material around the nanowires; and

depositing gate material around the gate dielectric material thereby forming a gate.

4. The method according to claim 3, the method further comprising:

forming a source at one side of the nanowire material next to the dummy gate or the gate; and

forming a drain at an opposite end of the nanowire material at an opposite side of the dummy gate or the gate.

5. The method according to claim 1, wherein providing the spacer material comprises filling the spacer material from a bottom portion of the void toward a top portion of the void.

6. The method according to claim 1, wherein providing the spacer material comprises (i) a first step where a first material is filled bottom up and (ii) a second step comprising a continuous fill with a second material.

7. The method according to claim 1, wherein providing the spacer material comprises refilling the void and/or a trench with at least one of:

a liner, FCVD oxide or spin on material.

8. The method according to claim 1, wherein the at least partly removing the sacrificial material is done by isotropic etching.

9. The method according to claim 1, wherein providing the semiconductor structure comprises depositing a stack of layers on a substrate, the stack of layers comprising layers of sacrificial material alternated with layers of nanowire material and forming at least one fin in the stack of layers.

10. The method according to claim 9, wherein the depositing the stack of layers on the substrate comprises depositing at least two layers of nanowire material.

11. The method according to claim 10, wherein the depositing the stack of layers on the substrate comprises depositing at least three layers of nanowire material.

12. The method according to claim 9, wherein the depositing the stack of layers on the substrate comprises depositing layers of nanowire material, wherein the layers of nanowire material comprise at least one of Silicon, SiGe, Ge, InGaAs, or III-V material.

13. The method according to claim 12, wherein the depositing the stack of layers on the substrate comprises depositing Ge nanowire material layers and SiGe sacrificial material layers.

14. The method according to claim 12, wherein the depositing the stack of layers on the substrate comprises depositing Si nanowire material layers and SiGe sacrificial material layers.

15. The method according to claim 1, wherein providing the spacer material comprises depositing at least one of:

silicon nitride, SiC;

O, an FCVD oxide, or SiN.

16. A method of forming a semiconductor device, the method comprising:

providing a semiconductor structure comprising at least one fin, the at least one fin comprising a stack of layers of a sacrificial material alternated with layers of a nanowire material, the semiconductor structure comprising a dummy gate partly covering the stack of layers of the at least one fin;

at least partly removing the sacrificial material, in between the layers of the nanowire material, next to the dummy gate so as to form a void;

forming an internal spacer by providing spacer material within the void; and

after forming the internal spacer, (i) removing the dummy gate and (ii) selectively removing the sacrificial material in a part of the fin which was covered by the dummy gate, so as to release nanowires.

17. The method according to claim 16, further comprising:

depositing gate dielectric material around the nanowires; and

depositing gate material around the gate dielectric material thereby forming a gate.

18. The method according to claim 17, further comprising:

forming a source at one side of the nanowire material next to the dummy gate or the gate; and

forming a drain at an opposite end of the nanowire material at an opposite side of the dummy gate or the gate.

19. The method according to claim 16, wherein forming the internal spacer comprises filling the spacer material from a bottom portion of the void toward a top portion of the void.

20. The method according to claim 16, wherein forming the internal spacer comprises (i) a first step where a first material is filled from a bottom portion of the void toward a top portion of the void and (ii) a second step comprising a continuous fill with a second material.