Noise Reduction for Overlay Control

• US 20180173110A1
• Filed: 07/07/2017
• Published: 06/21/2018
• Est. Priority Date: 12/15/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hu, Weimin, Chang, Yang-Hung, Chen, Kai-Hsiung, Hu, Chun-Ming, Ke, Chih-Ming
• Granted Patent: US 10,281,827 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Abstract

The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

Claims

1. A method, comprising:

patterning a substrate by a patterning tool;

collecting a plurality of overlay errors from a plurality of fields on the substrate;

identifying noise from the plurality of overlay errors, wherein the identifying of the noise includes applying a first filtering operation and a second filtering operation that is different from the first filtering operation;

grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors;

calculating an overlay compensation based on the set of filtered overlay errors; and

performing a compensation process to the patterning tool according to the overlay compensation.

2. The method of claim 1, wherein the identifying of the noise further includes:

identifying outliers from the plurality of overlay errors by applying the first filtering operation; and

identifying noise from the outliers by applying the second filtering operation.

3. The method of claim 2, wherein:

the first filtering operation is applied to each of the plurality of fields individually; and

the second filtering operation includes applying an inter-field correction model to the plurality of fields collectively.

4. The method of claim 3, wherein the second filtering operation further includes applying an intra-field correction model to each of the plurality of fields individually.

5. The method of claim 4, wherein:

the inter-field correction model is a correction-per-exposure (CPE) model; and

the intra-field correction model is an intra-field high order process correction (iHOPC) model.

6. The method of claim 2, wherein the identifying of the outliers includes, for each of the plurality of fields:

picking a reference overlay error; and

identifying overlay errors as outliers if values of the overlay errors are larger than a threshold determined by the reference overlay error.

7. The method of claim 2, wherein the identifying of the noise from the outliers includes:

determining overlay errors due to reticle effects from the plurality of overlay errors by calculating a residue according to the second filtering operation; and

determining the outliers that are not identified as overlay errors due to reticle effects as the noise.

8. The method of claim 7, wherein the calculating of the residue includes subtracting a sum of a value calculated by an inter-field correction model and another value calculated by an intra-field correction model from each of the plurality of overlay errors.

9. The method of claim 1, further comprising:

removing extra noise from the set of filtered overlay errors by applying a third filtering operation prior to the calculating of the overlay compensation, wherein the third filtering operation is different from the first and second filtering operations.

10. The method of claim 9, wherein the third filtering operation includes applying an inter-field high order process correction (HOPC) model.

11. The method of claim 10, wherein the removing of the extra noise includes removing an overlay error from the set of filtered overlay errors if a residue between a value of the overlay error and a value based on the HOPC model is larger than a threshold value.

12. The method of claim 10, wherein the HOPC model has an order equal to or less than 5.

13. The method of claim 1, wherein:

the substrate includes a semiconductor wafer;

the collecting of the plurality of overlay errors includes measuring a plurality of overlay marks on the semiconductor wafer; and

the performing of the compensation process to the patterning tool includes adjusting an optical parameter of a projection module of the patterning tool.

14. A method for overlay monitoring and control, the method comprising:

forming patterns on a wafer by a lithography system;

collecting an overlay error set from the patterns, wherein the overlay error set includes a plurality of overlay error subsets according to a field scheme of the wafer;

determining outliers from each of the plurality of overlay error subsets;

identifying the outliers that are not due to reticle effects as noise;

forming a filtered overlay error set by excluding the noise from the overlay error set;

removing extra noise from the filtered overlay error set by applying an inter-field correction model;

after the removing of the extra noise, generating an overlay compensation from the filtered overlay error set; and

adjusting at least one parameter of the lithography system according to the overlay compensation.

15. The method of claim 14, wherein the determining of the outliers from each of the plurality of overlay error subsets includes:

ranking overlay errors in each of the plurality of overlay error subsets; and

comparing the overlay errors to a threshold determined by a reference overlay error selected from each of the plurality of overlay error subsets.

16. The method of claim 14, further includes:

determining a plurality of overlay errors as overlay errors due to reticle effects by computing residues of the plurality of overlay errors according to a correction-per-exposure (CPE) model and an intra-field high order process correction (iHOPC) model.

17. A system for patterning and overlay control, the system comprising:

a patterning tool configured to form patterns on a wafer;

a metrology tool configured to measure overlay errors associated with the patterns in each field of the wafer; and

a controller module configured to read the overlay errors from the metrology tool, generate an overlay compensation, and feed the overlay compensation to the patterning tool to adjust a parameter of the patterning tool, wherein the generation of the overlay compensation includes;

identifying noise from the overlay errors by applying at least two filtering operations;

grouping the overlay errors that are not identified as noise into a set of filtered overlay errors;

removing extra noise from the set of filtered overlay errors by applying another filtering operation that is different from the at least two filtering operations; and

after the applying of the another filtering operation, calculating the overlay compensation from the set of filtered overlay errors.

18. The system of claim 17, wherein the at least two filtering operations include applying a ranking model, an inter-field correction model, and an intra-field correction model.

19. The system of claim 18, wherein the identifying of the noise from the overlay errors includes:

determining outliers from the overlay errors by applying the ranking model to each field of the wafer;

determining overlay errors due to reticle effects by calculating residues according to the inter-field correction model and the intra-field correction model; and

identifying the outliers that are not overlay errors due to reticle effects as noise.

20. The system of claim 17, wherein the another filtering operation includes applying an inter-field high order process correction (HOPC) model.