HARD RESET OVER I3C BUS

• US 20180173665A1
• Filed: 12/16/2016
• Published: 06/21/2018
• Est. Priority Date: 12/16/2016
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Mishra, Lalan Jee, Pitigoi-Aron, Radu, Wietfeldt, Richard Dominic
• Application Number:
  US15/382,102
• Publication Number:
  US 20180173665A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247

Abstract

Systems, methods, and apparatus are described that enable communication of in-band reset signals over a serial bus. A method performed at a slave device coupled to the serial bus includes configuring a reset controller to operate in one of plural modes, identifying a first reset pattern in signaling received from a multi-wire serial bus, complying with one or more transmissions defined by the protocol, asserting a reset input of a processing circuit in the slave device responsive to an identification of the first reset pattern when the reset controller is operated in a first mode, and ignoring the first reset pattern when the reset controller is operated in a second mode. The signaling received from the multi-wire serial bus may include one or more transmissions defined by a protocol used on the multi-wire serial bus. The reset controller may operate autonomously from the processing circuit in the first mode.

Claims

1. A method performed at a slave device coupled to a serial bus, comprising:

configuring a reset controller to operate in one of a plurality of modes;

identifying a first reset pattern in signaling received from a multi-wire serial bus, wherein the signaling received from the multi-wire serial bus includes one or more transmissions defined by a protocol used on the multi-wire serial bus;

complying with the one or more transmissions defined by the protocol;

asserting a reset input of a processing circuit in the slave device responsive to an identification of the first reset pattern when the reset controller is operated in a first mode; and

ignoring the first reset pattern when the reset controller is operated in a second mode,

wherein the reset controller operates autonomously from the processing circuit in the slave device.

2. The method of claim 1, wherein the first reset pattern is ignored by a second slave device that is operating in accordance with I2C protocols.

3. The method of claim 1, wherein configuring the reset controller comprises:

configuring one or more reset addresses in one or more reset address registers of the reset controller; and

configuring a gating value in a gate register of the reset controller,

wherein the reset controller operates in the second mode when the one or more reset address registers and the gate register have a same value, and

wherein the reset controller operates autonomously in the first mode when at least one reset address register and the gate register have different values.

4. The method of claim 1, wherein configuring the reset controller comprises:

configuring a reset address in a reset address register of the reset controller; and

configuring one or more gating values in one or more gate registers of the reset controller,

wherein the reset controller operates in the second mode when the reset address register and the one or more gate registers have a same value, and

wherein the reset controller operates autonomously in the first mode when the reset address register and at least one gate register have different values.

5. The method of claim 1, wherein the reset controller operates autonomously in the first mode after a power-on initialization of the slave device.

6. The method of claim 1, and further comprising:

modifying operation of the processing circuit in the slave device based on information encoded in a second reset pattern provided in the signaling received from the multi-wire serial bus.

7. The method of claim 6, further comprising:

decoding an identifier from the second reset pattern using a pulse width modulation decoder; and

asserting the reset input of the processing circuit in the slave device when the identifier is associated with the slave device.

8. The method of claim 6, and further comprising:

decoding a command code from the second reset pattern using a pulse width modulation decoder; and

modifying operation of the processing circuit in the slave device based on the command code.

9. The method of claim 8, and further comprising:

causing the processing circuit in the slave device to enter a sleep mode of operation in response to the command.

10. The method of claim 1, where the reset controller remains powered on and operating autonomously from the processing circuit in the slave device when the processing circuit in the slave device has entered a sleep mode of operation.

11. The method of claim 1, where the signaling received from the multi-wire serial bus includes one or more transmissions defined by an I3C protocol.

12. An apparatus, comprising:

a processing circuit;

a communication interface responsive to the processing circuit and adapted to be coupled to a multi-wire serial bus and configured to comply with one or more transmissions defined by protocols used on the multi-wire serial bus; and

a reset controller coupled to the serial bus and configurable to operate in one or more of a plurality of modes, wherein the reset controller is configured to;

identify a first reset pattern in signaling received from the multi-wire serial bus, wherein the signaling received from the multi-wire serial bus includes one or more transmissions defined by a first protocol used on the multi-wire serial bus;

cause a reset input of the processing circuit responsive to an identification of the first reset pattern when the reset controller is operated in a first mode; and

ignore the first reset pattern when the reset controller is operated in a second mode,

wherein the reset controller operates autonomously from the processing circuit.

13. The apparatus of claim 12, wherein the reset controller comprises:

a plurality of registers including a reset address register and a gate register; and

a comparator configured to provide an enable signal indicating whether certain bits in the reset address register match corresponding bits in the gate register,

wherein the reset controller is adapted to;

operate in the second mode when the one or more reset address registers and the gate register have a same value; and

operate autonomously in the first mode when at least one reset address register and the gate register have different values.

14. The apparatus of claim 12, and further comprising:

a pulse width modulation decoder configured to decode information encoded in a second reset pattern provided in the signaling received from the multi-wire serial bus.

15. The apparatus of claim 14, wherein the reset controller is adapted to:

assert the reset input of the processing circuit when the information includes an identifier associated with the apparatus.

16. The apparatus of claim 14, wherein reset controller is adapted to:

modify an operation of the processing circuit based on a command code included in the information.

17. A method performed at a host device coupled to a serial bus, comprising:

transmitting a first register value to a first slave device, wherein the first register value is selected to cause a reset controller in the first slave device to be configured to operate in a first mode;

transmitting a second register value to a second slave device, wherein the second register value is selected to cause a reset controller in the second slave device to be configured to operate in a second mode autonomously from a processing circuit in the second slave device;

providing a first reset pattern in signaling transmitted over the serial bus, wherein the first reset pattern is ignored by the first slave device and causes the reset controller in the second slave device to reset the processing circuit in the second slave device; and

transmitting register values to the first slave device and the second slave device that are selected to cause respective reset controllers in the first slave device and the second slave device to be configured to operate in the second mode autonomously from their respective processing circuits,

wherein the signaling includes one or more transmissions defined by a protocol used on the serial bus.

18. The method of claim 17, wherein the first reset pattern is ignored by a second slave device that is operating in accordance with I2C protocols.

19. The method of claim 17, wherein:

the first register value comprises a gating value identical to a first identifier maintained by the reset controller in the first slave device;

the second register value comprises a gating value identical to a second identifier maintained by the reset controller in the second slave device; and

modes of operation of reset controllers in the first slave device and the second slave device are determined based on a comparison of respective identifiers and corresponding gating values.

20. The method of claim 17, wherein the reset controller of the first slave device is configured to operate in the second mode autonomously from the processing circuit in the second slave device after a power-on initialization of the first slave device.

21. The method of claim 17, and further comprising:

providing a second reset pattern in the signaling transmitted over the serial bus; and

encoding information in the second reset pattern that is configured to cause modification of operation of a processing circuit in at least one slave device.

22. The method of claim 21, wherein encoding information in the second reset pattern comprises:

encoding an identifier using a pulse width modulation encoder,

wherein the identifier is selected to cause an autonomous reset controller in the at least one slave device to reset a processing circuit in the at least one slave device.

23. The method of claim 21, wherein encoding information in the second reset pattern comprises:

encoding a command code using a pulse width modulation encoder,

wherein the command code is selected to cause an autonomous reset controller in the at least one slave device to modify an operation of a processing circuit in the at least one slave device.

24. The method of claim 23, wherein the command code is selected to cause the processing circuit in the at least one slave device to enter a sleep mode of operation in response to the command.

25. The method of claim 17, where the signaling is transmitted over the serial bus includes one or more transmissions defined by an I3C protocol.

26. A processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

transmit a first register value to a first slave device coupled to a serial bus, wherein the first register value is selected to cause a reset controller in the first slave device to be configured to operate in a first mode;

transmit a second register value to a second slave device coupled to the serial bus, wherein the second register value is selected to cause a reset controller in the second slave device to be configured to operate in a second mode autonomously from a processing circuit in the second slave device;

provide a first reset pattern in signaling transmitted over the serial bus, wherein the first reset pattern is ignored by the first slave device and causes the reset controller in the second slave device to reset the processing circuit in the second slave device; and

transmit register values to the first slave device and the second slave device that are selected to cause respective reset controllers in the first slave device and the second slave device to be configured to operate in the second mode autonomously from their respective processing circuits,

wherein the signaling includes one or more transmissions defined by a protocol used on the serial bus.

27. The storage medium of claim 26, further comprising instructions that cause the at least one processing circuit to:

provide a second reset pattern in the signaling transmitted over the serial bus; and

encode information in the second reset pattern that is configured to cause modification of operation of a processing circuit in at least one slave device.

28. The storage medium of claim 26, further comprising instructions that cause the at least one processing circuit to:

encode an identifier using a pulse width modulation encoder,

wherein the identifier is selected to cause an autonomous reset controller in at least one slave device to reset a processing circuit in at least one slave device.

29. The storage medium of claim 26, further comprising instructions that cause the at least one processing circuit to:

encode a command code using a pulse width modulation encoder,

wherein the command code is selected to cause an autonomous reset controller in at least one slave device to modify an operation of a processing circuit in the at least one slave device.

30. The storage medium of claim 29, wherein the command code is selected to cause the processing circuit in the least one slave device to enter a sleep mode of operation in response to the command.