INTEGRATED CIRCUIT FOR QUADRUPLE PATTERNING LITHOGRAPHY, AND COMPUTING SYSTEM AND COMPUTER-IMPLEMENTED METHOD FOR DESIGNING INTEGRATED CIRCUIT

• US 20180173837A1
• Filed: 10/25/2017
• Published: 06/21/2018
• Est. Priority Date: 12/16/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: WON, HYO-SIG, JANG, MYUNG-SOO, PARK, HYOUN-SOO, CHO, DA-YEON
• Granted Patent: US 10,621,300 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/68 Preparation processes not covered by groups G03F1/20 - G03F1/50
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 1/76 Patterning of masks by imaging
• CPC Class Codes: G03F 7/70283 Mask effects on the imaging process
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/31144 using masks

Abstract

A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.

Claims

1. A computer-implemented method comprising:

placing standard cells based on design data defining an integrated circuit;

generating a layout of the integrated circuit by performing colorless routing, wherein first, second, third, and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells;

storing the generated layout to a computer-readable storage medium,

wherein the space constraints define minimum spaces between the first, second, third and fourth patterns;

assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively;

generating masks based on the layout; and

manufacturing a semiconductor device by using the generated masks,

wherein a space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.

2. The method of claim 1, wherein the masks includes first, second, third and fourth masks, and the first, second, third and fourth colors respectively correspond to the first, second, third and fourth masks.

3. The method of claim 1, wherein the generating of the layout comprises receiving a technology file including the space constraints, and performing the colorless routing based on the received technology file.

4. The method of claim 1, wherein the first and second patterns extend in a first direction and are adjacent to each other in a second direction perpendicular to the first direction, and

the space constraints comprise a first space constraint that defines a minimum space between the first and second patterns as a first space between patterns of the first, second, third and fourth patterns to which different colors are assigned.

5. The method of claim 4, wherein the first space is a minimum side-to-side space between patterns of the first, second, third and fourth patterns to which different colors are assigned.

6. The method of claim 4, wherein the space constraints further comprise a second space constraint that defines a minimum comer-to-comer space between patterns of the first, second, third and fourth patterns to which different colors are assigned.

7. The method of claim 4, wherein the quadruple patterning lithography layer is a bi-directional layer,

the third pattern extends in the first direction and is substantially aligned with the first pattern or the second pattern in the first direction, and

the space constraints further comprise a third space constraint that defines a minimum space between the first or second pattern and the third pattern as a second space between patterns of the first, second, third and fourth patterns to which a same color is assigned.

8. The method of claim 7, wherein the second space is a minimum tip-to-tip space between the patterns of the first, second, third and fourth patterns to which the same color is assigned.

9. The method of claim 7, wherein the fourth pattern extends in the second direction, and

the space constraints further comprise a fourth space constraint that defines a minimum space between the fourth pattern and each of the first through third patterns as a third space between the patterns of the first, second, third and fourth patterns to which the same color is assigned.

10. The method of claim 9, wherein the third space is a minimum tip-to-side space between the patterns of the first, second, third and fourth patterns to which the same color is assigned.

11. The method of claim 4, wherein the quadruple patterning lithography layer is a rani-directional layer,

the third and fourth patterns extend in the first direction and are respectively aligned with the first and second patterns in the first direction, and

the space constraints further comprise a third space constraint that defines a minimum space between the first and third patterns and a minimum space between the second and fourth patterns as a second space between the patterns of the first, second, third and fourth patterns to which different colors are assigned.

12. The method of claim 11, wherein the second space is a minimum tip-to-tip space between the patterns of the first, second, third and fourth patterns to which different colors are assigned.

13. A computing system comprising:

a memory configured to store procedures for designing an integrated circuit; and

a processor configured to access the memory and to execute the procedures for designing the integrated circuit,

wherein the procedures for designing the integrated circuit comprise;

a placer configured to place standard cells based on design data defining the integrated circuit, and

a router configured to perform colorless routing, wherein the colorless routing arranges first, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer, based on space constraints, on the placed standard cells,

wherein the space constraints define minimum spaces between the first, second, third and fourth patterns so that a color violation does not occur between the first, second, third and fourth patterns.

14. The system of claim 13, wherein the procedures further comprise a color decomposer configured to assign first, second, third and fourth colors to the first through fourth patterns, respectively.

15. The system of claim 13, wherein the router is further configured to receive a technology file including the space constraints and to perform the colorless routing based on the received technology file.

16-26. -26. (canceled)

27. A computer-implemented method comprising:

receiving a technology file,

wherein the technology file includes a set of minimum space constraints comprising;

a minimum side-to-side space between first, second, third and fourth patterns;

a minimum corner-to-corner space between the first, second, third and fourth patterns; and

a minimum tip-to-tip space between the first, second, third and fourth patterns; and

forming an integrated circuit including the first, second, third and fourth patterns having pattern spacing meeting or exceeding the minimum space constraints, wherein a space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the minimum space constraints indicates a color violation.

28. The method of claim 27, wherein at least two of the first, second, third and fourth. patterns have different colors from each other.

29. The method of claim 28, wherein each of the first, second, third and fourth patterns have different colors from each other.

30. The method of claim 29, wherein the minimum space constraints further comprises a minimum tip-to-side space between the first, second, third and fourth patterns.

31. The method of claim 27, wherein each of the first, second, third and fourth patterns is formed by a respective first, second, third or fourth mask.