Semiconductor Memory Having Volatile and Multi-Bit Non-Volatile Functionality and Method of Operating

• US 20180174654A1
• Filed: 02/10/2018
• Published: 06/21/2018
• Est. Priority Date: 04/08/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 10,210,934 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Claims

1-21. -21. (canceled)

22. An integrated circuit comprising:

a memory array comprising a plurality of rows and columns of semiconductor memory cells, a plurality of said memory cells each comprising;

a floating body region to store charge as volatile memory;

first and second locations adjacent said floating body region, said first and second locations spaced apart from one another;

a trapping layer positioned in between the first and second locations and above a surface of the floating body region;

the trapping layer comprising first and second storage locations being configured to store charge as nonvolatile memory independently of one another; and

a control gate positioned above the trapping layer;

wherein said memory cell is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body;

wherein when a first memory cell of said plurality of said memory cells stores a first charge as volatile memory and a second memory cell of said plurality of said memory cells stores a second charge as volatile memory different from said first charge, one of said first and second storage locations of said first memory cell interacting with said floating body of said first memory cell stores a first non-volatile data upon receiving transfer of data stored as said volatile memory and one of said first and second storage locations of said second memory cell interacting with said floating body of said second memory cell stores a second non-volatile data different from said first non-volatile data; and

a control circuit to perform said transfer of data stored in volatile memory to one of said first and second storage locations.

23. The integrated circuit of claim 22, further comprising control terminals electrically connecting the rows of said memory array, respectively, to each said control gate.

24. The integrated circuit of claim 22, wherein said plurality of memory cells each comprise a buried layer, electrically connected to an additional control terminal that is shared among at least two of said plurality of memory cells.

25. The integrated circuit of claim 22, further comprising a buried insulator layer bounding a bottom of said floating body.

26. The integrated circuit of claim 22, further comprising control terminals defining the columns of said memory array.

27. The integrated circuit of claim 26, wherein the number of said control terminals defining the columns is equal to twice the number of the columns.

28. The integrated circuit of claim 26, wherein the number of said control terminals defining the columns is equal to the number of the columns plus one.

29. The integrated circuit of claim 22, wherein said memory cells function as binary cells.

30. The integrated circuit of claim 22, wherein said memory cells function as multi-level cells.

31. An integrated circuit comprising:

a memory array comprising a plurality of rows and columns of semiconductor memory cells, a plurality of said memory cells each comprising;

a floating body region to store charge as volatile memory;

first and second locations adjacent said floating body region, said first and second locations spaced apart from one another;

a trapping layer positioned in between first and second locations and above a surface of the floating body region, the trapping layer comprising first and second storage locations being configured to store charge as nonvolatile memory independently of one another; and

a control gate positioned above the trapping layer;

wherein each of said plurality of memory cells is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body region;

wherein when a first memory cell of a plurality of said memory cells stores a first non-volatile data and a second memory cell of said plurality of said memory cells stores a second non-volatile data different from said first non-volatile data, said charge stored in said floating body region of said first memory cell is different from said charge stored in said floating body region of said second memory cell upon restoration of power to said memory cells; and

a control circuit configured to perform a restore operation to transfer said first non-volatile data to volatile data as said charge stored in said floating body region of said first memory cell and to transfer said second non-volatile date to volatile data as said charge stored in said floating body region of said second memory cell.

32. The integrated circuit of claim 31, further comprising control terminals electrically connecting the rows of said memory array, respectively, to said control gates.

33. The integrated circuit of claim 31, wherein said plurality of memory cells each comprise a buried layer, electrically connected to an additional control terminal that is shared among at least two of said plurality of memory cells.

34. The integrated circuit of claim 31, further comprising a buried insulator layer bounding a bottom of said floating body.

35. The integrated circuit of claim 31, further comprising control terminals defining the columns of said memory array.

36. The integrated circuit of claim 35, wherein the number of said control terminals defining the columns is equal to twice the number of the columns.

37. The integrated circuit of claim 35, wherein the number of said control terminals defining the columns is equal to the number of the columns plus one.

38. The integrated circuit of claim 31, wherein said memory cells function as binary cells.

39. The integrated circuit of claim 31, wherein said memory cells function as multi- level cells.