Semiconductor package and method for fabricating a semiconductor package

• US 20180174935A1
• Filed: 12/12/2017
• Published: 06/21/2018
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: CHONG, Hock Heng, CHAN, Sook Woon, CHIANG, Chau Fatt, CHUNG, Khar Foong, FANG, Chee Hong, MUHAMMAD, Muhammat Sanusi, NG, Mei Chin, NG, Yean Seng, POK, Pei Luan, WANG, Choon Huey
• Granted Patent: US 10,490,470 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68304 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 2933/005 : relating to encapsulations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 33/54 : having a particular shape
• CPC Class Codes: H01L 33/642 : characterized by the shape

Abstract

A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the carrier and fabricating an encapsulation body covering the semiconductor chip.

Claims

1. A method of fabricating a semiconductor package, the method comprising:

providing a carrier;

fabricating an opening in the carrier;

attaching a semiconductor chip to the carrier; and

fabricating an encapsulation body covering the semiconductor chip.

2. The method of claim 1, wherein the opening is configured to relieve the semiconductor package from stress.

3. The method of claim 2, wherein the stress is based on a difference between the coefficients of thermal expansion of the carrier and the semiconductor chip.

4. The method of claim 1, wherein the fabricating of the opening in the carrier comprises at least one of cutting and drilling through the carrier.

5. The method of claim 4, wherein the at least one of cutting and drilling is performed using a laser.

6. The method of one claim 1, further comprising:

attaching the carrier to a temporary carrier prior to fabricating the opening.

7. The method of claim 1, further comprising:

applying a paste onto the carrier prior to fabricating the opening, wherein the paste is applied at the designated position of the opening.

8. The method of claim 1, wherein the opening comprises a hole or a trench.

9. The method of claim 1, wherein the opening comprises a trench that separates the carrier into a first segment and a second segment.

10. The method of claim 9, further comprising:

attaching the carrier to a temporary carrier prior to fabricating the trench, wherein the temporary carrier is configured to keep the first segment and the second segment in a defined position relative to each other.

11. The method of claim 9, further comprising:

applying a paste onto the carrier prior to fabricating the trench, the paste being configured to keep the first and second segments in a defined position relative to each other.

12. The method of claim 1, wherein the semiconductor chip comprises a photo active area and wherein the opening is configured to let light pass between the photo active area and the outside of the semiconductor package.

13. A semiconductor package, comprising:

a carrier comprising an opening;

a semiconductor chip attached to the carrier; and

an encapsulation body covering the semiconductor chip,

wherein the opening is configured to relieve the semiconductor package from stress.

14. The semiconductor package of claim 13, wherein the carrier comprises one or more of a leadframe, a laminate, an epoxy, an epoxy mold compound, a thermoset plastic, or a fiber-reinforced plastic.

15. The semiconductor package of claim 13, wherein the opening is at least partially filled with the encapsulation body.

16. The semiconductor package of claim 13, wherein the opening is at least partially filled with a paste of dielectric material that is different from the material of the encapsulation body.

17. The semiconductor package of claim 16, wherein the paste comprises a polymer.

18. The semiconductor package of claim 17, wherein the polymer comprises silicone.

19. An optoelectronic semiconductor package, comprising:

a carrier comprising an opening;

a semiconductor chip comprising a photo active area and attached to the carrier, wherein the photo active area faces the opening;

an optically transparent paste arranged in the opening; and

an encapsulation body covering the semiconductor chip,

wherein the optically transparent paste comprises a material that is different from the encapsulation body.

20. The optoelectronic semiconductor package of claim 19, wherein the carrier comprises one or more of a leadframe, a laminate, an epoxy, an epoxy mold compound, a thermoset plastic, or a fiber-reinforced plastic.