SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

• US 20180175101A1
• Filed: 12/20/2017
• Published: 06/21/2018
• Est. Priority Date: 12/20/2016
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: Ho, Yen-Shih, Liu, Tsang-Yu, Lin, Chia-Sheng, Lai, Chaung-Lin
• Granted Patent: US 10,461,117 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2221/68386 Separation by peeling
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 : Wafer level processing
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

Claims

1. A method for manufacturing semiconductor structure, comprising:

(a) adhering a first carrier to a first surface of a wafer by a first temporary bonding layer;

(b) etching a second surface of the wafer facing away from the first carrier to form at least one through hole and at least one trench, wherein a conductive pad of the wafer is exposed through the through hole;

(c) forming an isolation layer on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench;

(d) adhering a second carrier to the second surface of the wafer by a second temporary bonding layer, wherein the through hole and the trench are covered by the second carrier; and

(e) removing the first carrier and the first temporary bonding layer.

2. The method for manufacturing semiconductor structure of claim 1, further comprising:

forming a redistribution layer on the isolation layer and the conductive pad.

3. The method for manufacturing semiconductor structure of claim 1, wherein step (a) comprises:

irradiating the first temporary bonding layer by a first ultraviolet light with a first wavelength, thereby enabling the first temporary bonding layer to form an adhesive force.

4. The method for manufacturing semiconductor structure of claim 3, wherein step (e) comprises:

irradiating the first temporary bonding layer by a second ultraviolet light with a second wavelength, thereby eliminating the adhesive force of the first temporary bonding layer, wherein the second wavelength is different from the first wavelength.

5. The method for manufacturing semiconductor structure of claim 2, wherein step (d) comprises:

irradiating the second temporary bonding layer by a first ultraviolet light with a first wavelength, thereby enabling the second temporary bonding layer to form an adhesive force.

6. The method for manufacturing semiconductor structure of claim 5, after step (e), the method further comprising:

disposing an optical element that has a dam element on the first surface of the wafer, thereby enabling the dam element to be located between the optical element and the first surface, wherein the dam element covers the conductive pad and the trench, and surrounds an image sensing area of the wafer.

7. The method for manufacturing semiconductor structure of claim 6, further comprising:

removing the second carrier and the second temporary bonding layer after the optical element is disposed on the first surface of the wafer.

8. The method for manufacturing semiconductor structure of claim 7, wherein the removing the second carrier comprises:

irradiating the second temporary bonding layer by a second ultraviolet light with a second wavelength, thereby eliminating the adhesive force of the second temporary bonding layer, wherein the second wavelength is different from the first wavelength.

9. The method for manufacturing semiconductor structure of claim 7, further comprising:

forming an insulating layer that covers the redistribution layer, the through hole, and the trench after the second carrier and the second temporary bonding layer are removed.

10. The method for manufacturing semiconductor structure of claim 9, wherein the forming the insulating layer comprises:

filling the trench with the insulating layer.

11. The method for manufacturing semiconductor structure of claim 9, further comprising:

patterning the insulating layer, thereby enabling the insulating layer has at least one opening that exposes the redistribution layer.

12. The method for manufacturing semiconductor structure of claim 11, further comprising:

forming a conductive structure on the redistribution layer that is in the opening of the insulating layer.

13. The method for manufacturing semiconductor structure of claim 12, further comprising:

dicing the optical element, the dam element, and the insulating layer in a vertical direction along the trench to form at least one chip package after the conductive structure is formed.

14. The method for manufacturing semiconductor structure of claim 6, wherein the optical element is made of glass.

15. The method for manufacturing semiconductor structure of claim 6, wherein a light transmittance of the optical element is greater than a light transmittance of the first carrier, and is greater than a light transmittance of the second carrier.

16. The method for manufacturing semiconductor structure of claim 6, wherein a thickness of the optical element is smaller than a thickness of the first carrier, and is smaller than a thickness of the second carrier.

17. The method for manufacturing semiconductor structure of claim 6, wherein the optical element is an anti-reflection (AR) glass or an infrared (IR) glass.

18. The method for manufacturing semiconductor structure of claim 6, wherein the optical element is made of a material comprising fuel silica.

19. A semiconductor structure, comprising:

a first chip having a surface that has a first conductive pad and a first image sensing area;

a first dam element covering the first conductive pad and surrounding the first image sensing area; and

an optical element disposed on the first dam element and covering the first image sensing area, wherein the optical element has a top surface and a bottom surface, the bottom surface facing the first image sensing area, the top surface facing away from the first image sensing area, and the top surface has curved shape.

20. The semiconductor structure of claim 19, wherein the optical element comprises:

a support portion located on the first dam element and having the bottom surface; and

a lens portion located on the support portion, having the top surface, and covering the first image sensing area.

21. The semiconductor structure of claim 19, further comprising:

a second chip next to the first chip, wherein a surface of the second chip has a second conductive pad and a second image sensing area; and

a second dam element covering the second conductive pad and surrounding the second image sensing area, wherein the optical element extends onto the second dam element and covers the second image sensing area, and a portion of the bottom surface of the optical element faces the second image sensing area, and a portion of the top surface of the optical element faces away from the second image sensing area.

22. The semiconductor structure of claim 21, wherein the optical element comprises:

a support portion located on the first dam element and the second dam element, and having the bottom surface; and

two lens portions located on the support portion, having the top surface, and respectively covering the first image sensing area and the second image sensing area.

23. The semiconductor structure of claim 19, wherein the optical element comprises:

a support portion located on the first dam element and surrounding an accommodating space; and

a plurality of lens portions physically connected to the support portion and located in the accommodating space, and overlapping the first image sensing area, wherein one of the lens portions has the top surface, and one of the lens portions has the bottom surface.