THIN-FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

• US 20180175206A1
• Filed: 01/03/2017
• Published: 06/21/2018
• Est. Priority Date: 12/16/2016
• Status: Active Grant

• Current Assignee: Chunghwa Picture Tubes Limited
• Original Assignee: Chunghwa Picture Tubes Limited
• Inventors: Kao, Chin-Tzu, Wang, Chung-Hsu
• Granted Patent: US 10,181,528 B2
• Time in Patent Office: Days
• CPC Class Codes: C23C 16/042 using masks
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: C23C 16/505 using radio frequency discharges
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The invention relates to a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor includes the following steps: an insulating layer is formed to cover a gate on a substrate; a semiconductor pattern having a first region and a second region is formed on the insulating layer; a plurality of island patterns is formed, wherein at least a portion of the plurality of island patterns is disposed on the semiconductor pattern, and the plurality of island patterns is separated from one another by a gap; and a source and a drain are formed to cover a portion of the plurality of island patterns and fill the gaps to respectively be electrically connected to the first region and the second region of the semiconductor pattern.

Claims

1. A manufacturing method of a thin-film transistor, comprising:

forming a gate on a substrate;

forming an insulating layer to cover the gate;

forming a semiconductor pattern on the insulating layer, wherein the semiconductor pattern has a first region and a second region opposite to each other;

forming a plurality of island patterns, wherein at least a portion of the plurality of island patterns is disposed on the semiconductor pattern, and the plurality of island patterns are separated from each other by gaps; and

forming a source and a drain to cover a portion of the plurality of island patterns and fill the gaps such that the source and the drain are respectively electrically connected to the first region and the second region of the semiconductor pattern.

2. The manufacturing method of the thin-film transistor of claim 1, wherein a method of forming the plurality of island patterns comprises a half-deposition method.

3. The manufacturing method of the thin-film transistor of claim 2, wherein a rate of forming a height of each of the island patterns is greater than 0 Å

/sec and less than or equal to 10 Å

/sec.

4. The manufacturing method of the thin-film transistor of claim 2, wherein a method of forming the plurality of island patterns comprises a plasma-enhanced chemical vapor deposition method, gases used in the plasma-enhanced chemical vapor deposition method comprise silane and nitrogen oxide, and process parameters of the plasma-enhanced chemical vapor deposition method comprise a silane flow rate between 80 sccm and 1600 sccm, a nitrogen oxide flow rate between 5000 sccm and 65000 sccm, a radio frequency power between 80 W and 2300 W, a pressure between 0.4 mbar and 0.6 mbar or between 750 mTorr and 1450 mTorr, and a temperature between 220 Celsius and 350 Celsius.

5. The manufacturing method of the thin-film transistor of claim 1, wherein the plurality of island patterns are randomly distributed on the first region and the second region of the semiconductor pattern.

6. The manufacturing method of the thin-film transistor of claim 1, wherein sizes of the plurality of island patterns are not consistent.

7. The manufacturing method of the thin-film transistor of claim 1, wherein a method of forming the plurality of island patterns comprises a chemical vapor deposition method, and the chemical vapor deposition method comprises:

disposing a shielding plate between the semiconductor pattern and a gas source, wherein the shielding plate has a plurality of holes, and a gas from the gas source passes through the plurality of holes of the shielding plate and forms a plurality of island patterns corresponding to the plurality of holes on the semiconductor pattern.

8. The manufacturing method of the thin-film transistor of claim 1, wherein the semiconductor pattern further has a third region connected between the first region and the second region, and the plurality of island patterns is further formed on the third region of the semiconductor pattern and a portion of the insulating layer exposed by the semiconductor pattern.

9. The manufacturing method of the thin-film transistor of claim 8, wherein a method of forming the source and the drain comprises:

forming a conductive layer to cover the plurality of island patterns, the first region, the second region, and the third region of the semiconductor pattern, and the portion of the insulating layer exposed by the semiconductor pattern; and

patterning the conductive layer using a wet etching process to form the source and the drain respectively covering the first region and second region and exposing the third region of the semiconductor pattern, wherein another portion of the plurality of island patterns located on the third region of the semiconductor pattern and the portion of the insulating layer is kept when the source and the drain are formed.

10. The manufacturing method of the thin-film transistor of claim 8, wherein a method of forming the source and the drain comprises:

forming a conductive layer to cover the plurality of island patterns, the first region, the second region, and the third region of the semiconductor pattern, and the portion of the insulating layer exposed by the semiconductor pattern; and

patterning the conductive layer using a dry etching process to form the source and the drain respectively covering the first region and the second region and exposing the third region of the semiconductor pattern, wherein another portion of the plurality of island patterns located on the third region of the semiconductor pattern and the portion of the insulating layer exposed by the semiconductor pattern, the source, and the drain is removed when the source and the drain are formed.

11. The manufacturing method of the thin-film transistor of claim 1, wherein the other portion of the plurality of island patterns is disposed at two sides of the semiconductor pattern and located on the insulating layer, and the source and the drain further cover the other portion of the plurality of island patterns.

12. The manufacturing method of the thin-film transistor of claim 1, wherein a material of the semiconductor pattern comprises a metal-oxide-semiconductor.

13. A thin-film transistor disposed on a substrate, wherein the thin-film transistor comprises:

a gate disposed on the substrate;

an insulating layer covering the gate;

a semiconductor pattern disposed on the insulating layer, wherein the semiconductor pattern has a first region and a second region opposite to each other;

a plurality of first island patterns and a plurality of second island patterns respectively disposed on the first region and the second region of the semiconductor pattern, wherein the plurality of first island patterns are separated from each other by first gaps, the plurality of second island patterns are separated from each other by second gaps, and a material of the first island patterns and the second island patterns is an insulating material;

a source and a drain, wherein the source covers the plurality of first island patterns and fills the first gaps to be electrically connected to the first region of the semiconductor pattern, and the drain covers the plurality of second island patterns and fills the second gaps to be electrically connected to the second region of the semiconductor pattern.

14. The thin-film transistor of claim 13, wherein the semiconductor pattern further has a third region connected between the first region and the second region, the source and the drain respectively cover the first region and the second region, the source and the drain expose the third region, and the thin-film transistor further comprises:

a plurality of third island patterns disposed on the third region of the semiconductor pattern, wherein the plurality of third island patterns are separated from each other by third gaps, and the third gaps expose a portion of the third region, and a material of the third second island patterns is an insulating material.

15. The thin-film transistor of claim 14, wherein the thin-film transistor further comprises:

a plurality of fourth island patterns and a plurality of fifth island patterns respectively disposed at two sides of the semiconductor pattern and located on the insulating layer, wherein the source and the drain further respectively cover the plurality of fourth island patterns and the plurality of fifth island patterns, and a material of the fourth island patterns and the fifth island patterns is an insulating material.

16. The thin-film transistor of claim 15, wherein the thin-film transistor further comprises:

a plurality of sixth island patterns disposed on the semiconductor pattern and a portion of the insulating layer exposed by the source and the drain, and a material of the second island patterns is an insulating material.

17. The thin-film transistor of claim 13, wherein the semiconductor pattern further has a third region connected between the first region and the second region, the source and the drain expose the third region of the semiconductor pattern, and the plurality of first island patterns and the plurality of second island patterns expose the third region of the semiconductor pattern and the portion of the insulating layer exposed by the semiconductor pattern, the source, and the drain.

18. The thin-film transistor of claim 17, wherein the thin-film transistor further comprises:

a plurality of fourth island patterns and a plurality of fifth island patterns respectively disposed at two sides of the semiconductor pattern and located on the insulating layer, wherein the source and the drain further respectively cover the plurality of fourth island patterns and the plurality of fifth island patterns.

19. The thin-film transistor of claim 13, wherein the plurality of first island patterns and the plurality of second island patterns are randomly distributed on the first region and the second region of the semiconductor pattern.

20. The thin-film transistor of claim 13, wherein sizes of the plurality of island patterns are not consistent, and sizes of the second island patterns are not consistent.