Hybrid LDPC-SEC/SECDED Decoding

• US 20180175885A1
• Filed: 12/19/2016
• Published: 06/21/2018
• Est. Priority Date: 12/19/2016
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Hanham, Paul, Bowman, Josh, Symons, David
• Application Number:
  US15/383,569
• Publication Number:
  US 20180175885A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1108 Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1174 Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2927 Decoding strategies
• CPC Class Codes: H03M 13/3738 with judging correct decoding
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing

Abstract

A solid state storage device, comprising a non-volatile memory configured to store data encoded into a plurality of encoded data groups, each encoded data group of the plurality being encoded using a BCH or Hamming parity scheme, the plurality of encoded data groups being collectively further encoded by a parity scheme using a Low Density Parity Check (LDPC) code, a non-volatile memory controller communicatively coupled to the non-volatile memory and configured to access the plurality of encoded data groups, a first decoder configured to first decode the plurality of encoded data groups by hard-decision decoding the parity in each encoded data group, and a second decoder commutatively coupled to the first decoder and configured to determine the data groups decoded by the first decoder that contain errors, and to decode the parity of the data groups that contain errors using likelihood-of-errors information that is input to the second decoder.

Claims

1. A solid state storage device, comprising:

a non-volatile memory configured to;

store further encoded data groups comprising a plurality of first encoded data groups collectively further encoded by a soft-decision parity scheme using a Low Density Parity Check (LDPC) code, each first encoded data group of the plurality being encoded using a hard decision parity scheme;

a non-volatile memory controller communicatively coupled to the non-volatile memory and configured to access the plurality of further encoded data groups; and

an integrated decoder, configured to;

decode the plurality of further encoded data groups to give first decoded data groups by hard-decision decoding the parity in each first encoded data group within the further encoded data groups;

generate log likelihood ratio (LLR) information to be associated with each of the first decoded data groups; and

iteratively further decode the first decoded data groups using the LLR information.

2. The solid state storage device of claim 1, further comprising:

a first decoder configured to decode the plurality of first encoded data groups within the further encoded data groups to generate the first decoded data groups;

an LLR module configured to receive the first decoded data groups and soft data derived from multiple reads of the non-volatile memory and generate LLR information; and

a processing module configured to iteratively decode the first decoded data groups using the LLR information.

3. The solid state storage device of claim 2, wherein the group and node processing module further comprises:

an LLR buffer configured to receive the LLR information from the LLR module, and wherein the LLR buffer is separately coupled to a variable node processing module and a check node processing module.

4. The solid state storage device of claim 3, wherein the variable node processing module further comprises a sub-decoder to decode the LLR information in the LLR buffer.

5. The solid state storage device of claim 4, wherein the sub-decoder is a hard-decision BCH decoder or a soft-decision Hamming code decoder.

6. The solid state storage device of claim 2, wherein the parity decoded by the first decoder is based on a BCH code or a Hamming code.

7. The solid state storage device of claim 1, wherein the hard-decision parity scheme is a single-error correcting (SEC) code or a single-error correcting double-error detecting (SECDED) code.

8. The solid state storage device of claim 7, wherein SEC or SECDED decoded data with one or more errors is fixed by the integrated decoder.

10. The solid state storage device of claim 8, wherein the integrated decoder independently uses LLR information as soft information in each iteration of decoding the parity.

25. The solid state storage device of claim 3, wherein the LLR module is configured to assign LLR values to the first decoded data groups according to whether the decoded output of the first decoder contains no errors or contains one error, or whether the first decoder does not converge to a solution.

26. The solid state storage device of claim 25, wherein the LLR information in the LLR buffer is decoded by the group and node processing module.

27. The solid state storage device of claim 26, wherein the iterative decoding by the group and node processing module is performed iteratively using soft decision decoding until an error free solution is obtained.

9. (canceled)

11. (canceled)

12. (canceled)

13. A method of decoding non-volatile memory of a memory system, the method comprising:

accessing, by a non-volatile memory controller, data stored in the non-volatile memory, the data encoded into a plurality of first encoded data groups, each data group of the plurality being encoded using a first parity scheme;

accessing, by the non-volatile memory controller, a plurality of further encoded data groups, each of the plurality of further data groups being one of the plurality of first encoded data groups further encoded by a second parity scheme using a Low Density Parity Check (LDPC) code;

decoding, by the non-volatile memory controller, the plurality of first encoded data groups to give first decoded data groups by hard-decision decoding the first parity in each first encoded data group;

generating, by the non-volatile memory controller, log likelihood ratio (LLR) information to be associated with each of the first decoded data groups; and

iteratively further decoding the first decoded data groups using the LLR information.

14. The method of claim 13, wherein each iteration of the iterative decoding further comprises:

distributing, by a variable node processing module, the LLR information to a check node processing module;

storing the LLR information in an LLR buffer;

performing, by a check node processing module, LDPC check node calculations;

transferring, by the check node processing module, updated LLR information to a variable node processing module via the LLR buffer;

decoding, by a sub-decoder within the variable node processing module, the updated LLR information.

15. The method of claim 14, further comprising:

terminating the iterative decoding when the sub-decoder decodes the updated LLR information with no errors.

17. The method of claim 15, wherein the sub-decoder is a hard-decision BCH decoder or a soft-decision Hamming code decoder.

18. The method of claim 13, wherein the parity decoded by the non-volatile memory controller is a BCH code or a Hamming code.

19. The method of claim 13, wherein the first parity scheme is a single-error correcting (SEC) code or a single-error correcting double-error detecting (SECDED) code.

16. (canceled)

20. (canceled)

21. (canceled)

22. (canceled)

23. (canceled)

24. (canceled)