SYSTEM ON CHIP HAVING INTEGRATED SOLID STATE GRAPHICS CONTROLLERS

• US 20180181520A1
• Filed: 04/28/2017
• Published: 06/28/2018
• Est. Priority Date: 12/23/2016
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Osqueizadeh, Nima
• Granted Patent: US 10,445,275 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247

Abstract

Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.

Claims

1. A solid state graphics (SSG) die, comprising:

a memory hub;

at least one graphics processing unit (GPU) connected to the memory hub;

a first memory architecture controller connected to the memory hub, the first memory architecture directly controlling access to at least one first memory architecture;

a second memory architecture controller associated with each GPU, each second memory architecture controller connected to the memory hub and at least one second memory architecture;

an expansion bus first memory architecture controller connected to the memory hub, the expansion bus first memory architecture controller being an endpoint for a host system; and

an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system,

wherein the memory hub, the first memory architecture controller, the second memory architecture controller, and the expansion bus first memory architecture controller facilitate data transactions between at least the at least one first memory architecture and the at least one second memory architecture in response to a data transfer command.

2. The SSG die of claim 1, wherein the die is a component on a SSG subsystem and the at least one first memory architecture and the at least one second memory architecture are located on the SSG subsystem.

3. The SSG die of claim 1, wherein the die is a component on a SSG package and the at least one first memory architecture and the at least one second memory architecture are located on the SSG package.

4. The SSG die of claim 1, wherein the die is a component on a SSG package and the SSG package is a component on a SSG subsystem, the at least one first memory architecture is located on the SSG package and the at least one second memory architecture is located on the SSG subsystem.

5. The SSG die of claim 1, wherein the die is a component on a SSG package and the SSG package is a component on a SSG subsystem, the at least one first memory architecture is located on the SSG subsystem and the at least one second memory architecture is located on the SSG package.

6. The SSG die of claim 1, wherein the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is local memory.

7. The SSG die of claim 1, wherein the expansion bus controller is one of an expansion bus interface controller and an expansion bus switch.

8. The SSG die of claim 1, wherein the die is a component on a SSG subsystem and the SSG subsystem is a SSG card.

9. The SSG subsystem of claim 8, wherein the die is a component on a SSG subsystem and the SSG system is located on a board hosting the host system.

10. A solid state graphics (SSG) subsystem, comprising:

a die; and

a package including the die,

wherein the die comprises;

a memory hub;

at least one graphics processing unit (GPU) connected to the memory hub;

first memory architecture controllers connected to the memory hub, each first memory architecture directly controlling access to at least one first memory architecture;

a second memory architecture controller associated with each GPU, each second memory architecture controller connected to the memory hub and at least one second memory architecture;

at least one expansion bus first memory architecture controller connected to the memory hub, each expansion bus first memory architecture controller being an endpoint for a host system; and

an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system, and

wherein the memory hub, the first memory architecture controllers, the second memory architecture controllers, and the expansion bus first memory architecture controllers facilitate data transactions between at least the at least one first memory architecture and at least one second memory architecture in response to a data transfer command.

11. The SSG subsystem of claim 10, wherein the at least one first memory architecture and the at least one second memory architecture are located on the SSG subsystem.

12. The SSG subsystem of claim 10, wherein the at least one first memory architecture and the at least one second memory architecture are located on the package.

13. The SSG subsystem of claim 10, wherein the at least one first memory architecture is located on the package and the at least one second memory architecture is located on the SSG subsystem.

14. The SSG subsystem of claim 10, wherein the at least one first memory architecture is located on the SSG subsystem and the at least one second memory architecture is located on the package.

15. The SSG subsystem of claim 10, wherein the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is local memory.

16. The SSG subsystem of claim 10, wherein the expansion bus controller is one of an expansion bus interface controller and an expansion bus switch.

17. The SSG subsystem of claim 10, wherein the SSG subsystem is a SSG card.

18. The SSG subsystem of claim 10, wherein the SSG subsystem is located on a board hosting the host system.