Techniques for Coalescing Doorbells in a Request Message
First Claim
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1. An apparatus comprising:
- circuitry for a computing platform, the circuitry to include a central processing unit (CPU) cache;
doorbell logic for execution by the circuitry to generate a plurality of doorbells targeted to a respective plurality of memory rings or queues for a device on the computing platform communicatively coupled with the circuitry via a link arranged to operate according to a peripheral component interconnect express (PCIe) specification;
combine logic for execution by the circuitry to combine the plurality of doorbells in a cache line structure that includes separate information for each doorbell; and
write logic for execution by the circuitry to write the cache line structure to the CPU cache in a single write operation to cause the plurality of doorbells to be posted to the respective plurality of memory rings or queues.
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Abstract
Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.
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Citations
22 Claims
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1. An apparatus comprising:
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circuitry for a computing platform, the circuitry to include a central processing unit (CPU) cache; doorbell logic for execution by the circuitry to generate a plurality of doorbells targeted to a respective plurality of memory rings or queues for a device on the computing platform communicatively coupled with the circuitry via a link arranged to operate according to a peripheral component interconnect express (PCIe) specification; combine logic for execution by the circuitry to combine the plurality of doorbells in a cache line structure that includes separate information for each doorbell; and write logic for execution by the circuitry to write the cache line structure to the CPU cache in a single write operation to cause the plurality of doorbells to be posted to the respective plurality of memory rings or queues. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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generating a plurality of doorbells targeted to a respective plurality of memory rings or queues for a device on a computing platform operating according to a peripheral component interconnect express (PCIe) specification; combining the plurality of doorbells in a cache line structure that includes separate information for each doorbell; and writing the cache line structure to a cache or buffer for a central processing unit (CPU) of the computing platform in a single write operation to cause the plurality of doorbells to be posted to the respective plurality of memory rings or queues. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system at a computing platform cause the system to:
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generate a plurality of doorbells targeted to a respective plurality of memory rings or queues for a device on the computing platform, the device to operate according to a peripheral component interconnect express (PCIe) specification; combine the plurality of doorbells in a cache line structure that includes separate information for each doorbell; and write the cache line structure to a cache or buffer for a central processing unit (CPU) of the computing platform in a single write operation to cause the plurality of doorbells to be posted to the respective plurality of memory rings or queues. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification