DUAL COMMUNICATION FREQUENCY RFID CIRCUIT EQUIPPED WITH A TAMPER-EVIDENT LOOP

• US 20180182217A1
• Filed: 12/05/2017
• Published: 06/28/2018
• Est. Priority Date: 12/22/2016
• Status: Active Grant

• Current Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Original Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Inventors: Lamothe, Christian, Muller, Paul, Stojanovic, Goran
• Granted Patent: US 10,152,863 B2
• Time in Patent Office: Days
• CPC Class Codes: G06K 19/0724 the arrangement being a circuit for communicating at a plurality of frequencies, e.g. for managing time multiplexed communication over at least two antennas of different types
• CPC Class Codes: G06K 19/07381 with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering
• CPC Class Codes: G08B 13/126 for a housing, e.g. a box, a safe, or a room
• CPC Class Codes: G08B 13/1445 with detection of interference with a cable tethering an article, e.g. alarm activated by detecting detachment of article, breaking or stretching of cable furniture, e.g. shelves for displaying merchandise, incorporating tethers to prevent theft A47F7/024, A47F5/0861
• CPC Class Codes: G08B 13/2448 Tag with at least dual detection means, e.g. combined inductive and ferromagnetic tags, dual frequencies within a single technology, tampering detection or signalling means on the tag
• CPC Class Codes: G08B 13/2477 Antenna or antenna activator circuit

Abstract

A dual communication frequency RFID circuit includes a logic unit for processing data signals received or transmitted at a first frequency by a first antenna or at a second frequency by a second antenna, and a unit for managing the state of a tamper loop linked to the integrated circuit by two connection terminals. The management unit includes a first low-pass filter linked to a first connection terminal, a second low-pass filter linked to a second connection terminal, a current source for supplying a current through the first low-pass filter, a switch linked at the output of the second low-pass filter, and a first inverter connected between the current source and the first low-pass filter for supplying an output signal for the state of the tamper loop to the logic unit.

Claims

1. A dual communication frequency RFID circuit, comprising a logic unit for processing data signals received or transmitted at a first frequency by a first antenna or at a second frequency by a second antenna, the first communication frequency being lower than the second communication frequency, the logic unit being connected to a unit for managing the state of a tamper loop linked to the integrated circuit by two connection terminals,

wherein the management unit comprises at least one first low-pass filter linked to a first connection terminal, at least one second low-pass filter linked to a second connection terminal, a current source for supplying a current through the first low-pass filter, a switch linked at the output of the second low-pass filter, and a first inverter connected between the current source and the first low-pass filter for supplying an output signal for the state of the tamper loop to the logic unit.

2. The RFID circuit according to claim 1, wherein the first low-pass filter and the second low-pass filter each comprise a first resistor and a first capacitor.

3. The RFID circuit according to claim 2, wherein the first low-pass filter is identical to the second low-pass filter with one and the same first resistor and one and the same first capacitor.

4. The RFID circuit according to claim 2, wherein the first resistor of the first low-pass filter is linked to the first connection terminal, wherein the first capacitor of the first low-pass filter is linked to a ground terminal or to a supply voltage terminal, wherein the first resistor of the second low-pass filter is linked to the second connection terminal, and wherein the first capacitor of the second low-pass filter is linked to a ground terminal or to a supply voltage terminal.

5. The RFID circuit according to claim 2, wherein a third low-pass filter is connected to the first low-pass filter between the first low-pass filter and the current source linked to an input of the first inverter, and wherein a fourth low-pass filter is connected to the second low-pass filter between the second low-pass filter and the switch.

6. The RFID circuit according to claim 5, wherein the third low-pass filter and the fourth low-pass filter each comprise a second resistor and a second capacitor, wherein the second resistor of the third low-pass filter is linked to a connecting node for the first resistor and the first capacitor of the first low-pass filter, wherein the second resistor of the fourth low-pass filter is linked to a connecting node for the first resistor and the first capacitor of the second low-pass filter, wherein a connecting node for the second resistor and the second capacitor of the third low-pass filter is linked to the current source and to an input of the first inverter, and wherein a connecting node for the second resistor and the second capacitor of the fourth low-pass filter is linked to the switch.

7. The RFID circuit according to claim 6, wherein the third low-pass filter is identical to the fourth low-pass filter with one and the same second resistor and one and the same second capacitor.

8. The RFID circuit according to claim 6, wherein a second PMOS transistor is linked between a supply voltage terminal and the connecting node for the second resistor and the second capacitor of the third low-pass filter, a gate of the second PMOS transistor being controlled by an activation signal.

9. The RFID circuit according to claim 1, wherein the switch is an MOS transistor linked at the output of the second low-pass filter and connected to a ground terminal.

10. The RFID circuit according to claim 9, wherein the MOS transistor is an NMOS transistor, a gate of which is controlled by an activation signal so as to put the NMOS transistor into the on state to allow the flow of a current originating from the current source, which current source is linked to a supply voltage terminal, when the tamper loop is not broken or absent.

11. The RFID circuit according to claim 10, wherein the current source comprises a third PMOS transistor in series with a fourth PMOS transistor, the third and fourth PMOS transistors being arranged between the supply voltage terminal and an input of the first inverter, wherein a gate of the third PMOS transistor is controlled by a control signal so as to put it into the on state, and wherein a gate of the fourth PMOS transistor is controlled by an inverse activation signal so as to put it into the on state.

12. The RFID circuit according to claim 8, wherein the logic unit supplies a logic input signal to the management unit, which management unit comprises a second inverter followed by a third inverter, the second inverter receiving the logic input signal so as to supply an inverse activation signal and the third inverter supplying the activation signal.

13. The RFID circuit according to claim 12, wherein the management unit comprises, between the supply voltage terminal and a reference current terminal, a sixth PMOS transistor linked in series with a seventh PMOS transistor, and an eighth PMOS transistor, connected in parallel with the sixth and seventh PMOS transistors, wherein a gate of the eighth PMOS transistor is linked to a connecting node for the sixth and seventh PMOS transistors so as to supply the control signal, wherein a gate of the sixth PMOS transistor is controlled by the activation signal, and wherein a gate of the seventh PMOS transistor is controlled by the inverse activation signal.

14. The RFID circuit according to claim 13, wherein the power supply of the first inverter is supplied by way of a fifth PMOS transistor connected to a supply voltage terminal, a gate of this fifth PMOS transistor being controlled by the control signal.

15. The RFID circuit according to claim 6, wherein the resistance of the second resistor of the third and fourth low-pass filters is greater than the resistance of the first resistor of the first and second low-pass filters, and wherein the capacitance of the first capacitor of the first and second low-pass filters is greater than the capacitance of the second capacitor of the third and fourth low-pass filters.