Methods of Forming Memory Arrays

• US 20180182765A1
• Filed: 12/27/2016
• Published: 06/28/2018
• Est. Priority Date: 12/27/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 10,014,302 B1
• Time in Patent Office: Days
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.

Claims

1. :

A method of forming a memory array, comprising;

forming a conductive wordline extending along a first direction, and along a rail of semiconductor material;

after forming the conductive wordline, patterning fins from the rail;

each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;

forming digit lines electrically coupled with the second pedestals; and

forming charge-storage devices electrically coupled with the first pedestals.

2. :

The method of claim 1 wherein the conductive wordline is over a conductive beam and is spaced from the conductive beam by dielectric material.

3. :

The method of claim 2 wherein the conductive wordline comprises metal, and wherein the conductive beam consists of conductively-doped silicon.

5. :

The method of claim 1 wherein the conductive wordline is one of a pair of conductive wordlines formed on opposing sides of the rail of semiconductor material.

21. :

The method of claim 1 further comprising forming a conductive beam extending beneath the conductive wordline.

22. :

The method of claim 21 wherein the conductive beam comprises a conductive material different from the conductive material of the conductive wordline.

4. :

The method of claim I wherein digit line material is formed over the rail prior to patterning the fins from the rail; and

wherein the digit line material is patterned into the digit lines with a same pattern utilized to pattern the fins from the rail.

6. :

The method of claim I wherein the rail of semiconductor material has a doped upper region; and

wherein said doped upper region becomes first source/drain regions in the first pedestals and second source/drain regions in the second pedestals.

7. :

A method of forming a memory array, comprising;

forming a pair of conductive wordlines extending along a first direction, and spaced from one another by a rail of semiconductor material;

forming at least one digit line material over the rail of semiconductor material;

slicing the at least one digit line material into digit lines with a pattern, and after the forming of the pair of the conductive wordlines, utilizing the same pattern during etching into the rail to form fins;

each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;

the digit lines being electrically coupled with the second pedestals; and

forming capacitors electrically coupled with the first pedestals.

8. :

The method of claim 7 wherein slicing the at least one digit line material into digit lines with a pattern includes slicing the digit line material into conductive interconnects with the pattern.

9. :

The method of claim 7 wherein the at least one digit line material includes a metal-containing composition over conductively-doped silicon.

10. :

The method of claim 7 wherein the conductive wordlines are over conductive beams, and are spaced from the conductive beams by dielectric material.

11. :

The method of claim 7 wherein the rail of semiconductor material has a heavily doped upper region; and

wherein said heavily-doped upper region becomes first source/drain regions in the first pedestals and second source/drain regions in the second pedestals.

23. :

The method of claim 7 further comprising forming a conductive beam extending beneath at least one of the conductive wordlines.

24. :

The method of claim 23 wherein the conductive beam comprises a conductive material different from the conductive material of the at least one conductive wordline.

12. :

A method of forming a memory array, comprising;

forming a plurality of conductive wordline pairs extending along a first direction and along rails of semiconductor material;

each conductive wordline pair comprising a first conductive wordline and a second conductive wordline, the first and second conductive wordlines of each of the conductive wordline pairs being spaced from one another by one of the rails of semiconductor material;

forming an expanse extending across the rails of semiconductor material;

the expanse comprising at least one digit line material;

slicing the expanse into a plurality of linear structures comprising the at least one digit line material;

the linear structures alternating between first linear structures and second linear structures;

the first linear structures being digit lines, the slicing utilizing a pattern, and after the forming of the plurality of the conductive wordline pairs. the same pattern being used during etching into the rails to form fins;

each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;

the digit lines being electrically coupled with the second pedestals;

dividing the at least one digit line material of the second linear structures into conductive interconnects electrically coupled with the first pedestals; and

forming capacitors electrically coupled with the conductive interconnects.

13. :

The method of claim 12 wherein;

capacitor materials are included within the expanse, and are over the at least one digit line material;

the capacitor materials are included within the first and second linear structures;

the capacitor materials are removed from the first linear structures; and

the capacitors materials of the second linear structures are divided into the capacitors while the at least one digit line material of the second linear structures is divided into the conductive interconnects.

25. :

The method of claim 12 further comprising forming a conductive beam extending beneath at least one of the conductive wordlines of the plurality of conductive wordline pairs.

26. :

The method of claim 25 wherein the conductive beam comprises a conductive material different from the conductive material of the at least one of the conductive wordlines of the plurality of conductive wordline pairs.

14-20. -20. (canceled)