PULSE-AMPLITUDE MODULATED HYBRID COMPARATOR CIRCUIT
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Abstract
Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.
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Citations
20 Claims
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1. (canceled)
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2. (canceled)
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3. (canceled)
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5. (canceled)
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6. An apparatus comprising:
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a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch; a second latch coupled to the output node of the first latch, the second latch including a complementary-metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal, the second output signal having a signal swing greater than a signal swing of the first output signal; the output node of the second latch is a first output node of the second latch, and the second latch further includes a second output node, and the second latch is configured to operate in a first mode to cause a differential voltage to develop at the first and second output nodes of the second latch, and to operate in a second mode to cause a level of the second output signal to move toward a voltage level at a first supply node and to cause a level of a signal at the second output node to move toward a voltage level of a second supply node; the second latch includes a pair of transistors having drains coupled to the first and second output nodes to form a differential transistor pair to cause the differential voltage to develop at the first and second output nodes of the second latch and the inverter includes an input node and an output node, the input node of the inverter coupled to the first output node of the second latch, and the output node of the inverter coupled to the second output node of the second latch; and the second latch includes a first additional transistor coupled between sources of the pair of transistors and a first supply node, and a second additional transistor coupled between the sources of the pair of transistors and a second supply node. - View Dependent Claims (4, 7, 8, 9)
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10. (canceled)
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11. An apparatus comprising:
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a first latch including; a first pair of transistors including gates coupled to first and second input nodes and drains coupled to first and second output nodes; a second pair of transistors including gates coupled to third and fourth input nodes and drains coupled to the first and second output nodes; a first transistor coupled between a node and the first output node; a second transistor coupled between the node and the second output node; a first resistor coupled between the first output node and a gate of the first transistor; a second resistor coupled between the second output node and a gate of the second transistor; and a current source coupled between the node and a supply node; and a second latch including; a third pair of transistors including gates coupled to the first and second output nodes, and drains coupled to third and fourth output nodes; a first inverter including an input node coupled to the third output node, and an output node coupled to the fourth output node; and a second inverter including an input node coupled to the fourth output node, and an output node coupled to the third output node.
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13. An apparatus comprising:
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a first latch including; a first pair of transistors including gates coupled to first and second input nodes and drains coupled to first and second output nodes; and a second pair of transistors including gates coupled to third and fourth input nodes and drains coupled to the first and second output nodes; and a second latch including; a third pair of transistors including gates coupled to the first and second output nodes, and drains coupled to third and fourth output nodes; a first inverter including an input node coupled to the third output node, and an output node coupled to the fourth output node a second inverter including an input node coupled to the fourth output node, and an output node coupled to the third output node; a first additional transistor coupled between sources of the third pair of transistors and a first supply node, and a second additional transistor coupled between the sources of the third pair of transistors and a second supply node; a third additional transistor coupled between the first and second inverters and the first supply node; and a fourth transistor coupled between the first and second inverters and the second supply node. - View Dependent Claims (12)
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14. An apparatus comprising:
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first and second input nodes to receive differential input signals; a first comparator circuit to compare the differential input signals with first reference signals; a second comparator circuit to compare the differential input signals with second reference signals; and a third comparator circuit to compare the differential input signals with third reference signals, each of the first, second, and third comparators including; a first latch to generate a differential signal at output nodes of the first latch based on values of the differential input signals and values of respective reference signals among the first, second, and third reference signals; a second latch to develop a differential signal at output nodes of the second latch during a first phase of a clock signal based on the differential voltage at the output nodes of the first latch, the second latch including a pair of clocked inverters to generate complementary-metal-oxide semiconductor (CMOS) output signals based on the differential signal at the output nodes of the second latch during a second phase of the clock signal, the pair of clocked inverters including a first inverter and a second inverter; a first transistor coupled between the first and second inverters and a first supply node, the first inverter including a gate to receive a first clock signal; and a second transistor coupled between the first and second inverters and a second supply node, the second inverter including a gate to receive a second clock signal. - View Dependent Claims (15, 16)
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17. An apparatus comprising:
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conductive lines on a circuit board; a first device coupled to the conductive lines; and a second device coupled to the conductive lines, the second device including a decision feedback equalizer (DFE), the DFE including a comparator circuit, the comparator circuit including; a first latch, the first latch including; a first pair of transistors including gates coupled to first and second input nodes and drains directly coupled to first and second output nodes; and a second pair of transistors including gates coupled to third and fourth input nodes and drains directly coupled to the first and second output nodes; and a second latch, the second latch including; a third pair of transistors including gates coupled to the first and second output nodes, and drains directly coupled to third and fourth output nodes; a first inverter including an input node coupled to the third output node, and an output node coupled to the fourth output node; and a second inverter including an input node coupled to the fourth output node, and an output node coupled to the third output node. - View Dependent Claims (18, 19, 20)
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Specification