SYSTEMS, METHODS, AND DEVICES FOR COMPONENT CARRIER MANAGEMENT IN CARRIER AGGREGATION SYSTEMS

• US 20180183560A1
• Filed: 02/02/2018
• Published: 06/28/2018
• Est. Priority Date: 04/08/2015
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: He, Hong, Heo, Youn Hyoung, Burbidge, Richard C.
• Application Number:
  US15/887,269
• Publication Number:
  US 20180183560A1
• Time in Patent Office: Days
• CPC Class Codes: H04L 5/001 the frequencies being arranged in component carriers
• CPC Class Codes: H04L 5/0098 Signalling of the activation or deactivation of component carriers, subcarriers or frequency bands
• CPC Class Codes: H04W 52/365 Power headroom reporting
• CPC Class Codes: H04W 76/34 Selective release of ongoing connections

Abstract

Systems and methods provide component carrier management in carrier aggregation systems. A medium access control (MAC) protocol data unit (PDU) includes an activation/deactivation MAC subheader and an activation/deactivation MAC control element (CE). A plurality of configured carriers are categorized into at least one cell group. Configured secondary cells (SCells) are activated/deactivated according to the activation/deactivation MAC subheader and the activation/deactivation MAC CE.

Claims

1. An apparatus for a user equipment (UE), comprising:

a memory to store a power headroom report (PHR) medium access control (MAC) control element; and

a baseband processor to;

generate a PHR MAC control element comprising;

one or more first octets comprising C fields, the number of first octets based on a number of serving cells (SCell) associated with the UE, each C field indicating a presence of power headroom (PH) per SCell; and

one or more second octets, each of the second octets comprising a PH value for an SCell corresponding to one of the C fields; and

encode a message for a wireless communication network comprising the PHR MAC control element.

2. The apparatus of claim 1, wherein the one or more first octets comprise:

one octet when there are less than eight SCells; and

four octets when there are eight or more SCells.

3. The apparatus of claim 2, wherein the one or more first octets comprise a single reserved bit.

4. The apparatus of claim 1, wherein the baseband processor is further to identify the PHR MAC control element in a subheader with a logical channel identifier.

5. The apparatus of claim 1, wherein the one or more second octets are arranged with respect to one another based on index values of associated SCells.

6. The apparatus of claim 1, wherein the one or more second octets comprise an octet comprising a Type 2 PH field immediately after the one or more first octets.

7. The apparatus of claim 1, wherein the PHR MAC control element has a variable size.

8. The apparatus of claim 1, wherein the memory is further to store PH measurements.

9. The apparatus of claim 1, wherein the PHR MAC control element is an extended PHR MAC control element.

10. The apparatus of claim 1, wherein the PHR MAC control element is a dual connectivity PHR MAC control element.

11. A machine readable storage medium including machine-readable instructions that, when executed by one or more processors of an evolved node B (eNB), cause the one or more processors to perform operations comprising:

decode a first message from user equipment (UE) comprising a PHR MAC control element;

identify one or more first octets in the PHR MAC control element comprising C fields, the number of first octets based on a number of serving cells (SCell) associated with the UE, each C field indicating a presence of power headroom (PH) per SCell; and

identify one or more second octets in the PHR MAC control element comprising PH values for SCells indicated as comprising PH by the C fields; and

encode a second message to configure the UE based on the PHR MAC control element.

12. The machine readable storage medium of claim 11, wherein the one or more first octets comprise:

one octet when there are less than eight SCells; and

four octets when there are eight or more SCells.

13. The machine readable storage medium of claim 12, wherein the one or more first octets comprise a single reserved bit.

14. The machine readable storage medium of claim 11, wherein the machine-readable instructions further cause the one or more processors to identify the PHR MAC control element in a subheader with a logical channel identifier.

15. The machine readable storage medium of claim 11, wherein the one or more second octets are arranged with respect to one another based on index values of associated SCells.

16. The machine readable storage medium of claim 11, wherein the one or more second octets comprise an octet comprising a Type 2 PH field immediately after the one or more first octets.

17. The machine readable storage medium of claim 11, wherein the PHR MAC control element has a variable size.

18. The machine readable storage medium of claim 11, wherein the PHR MAC control element is one of an extended PHR MAC control element or a dual connectivity PHR MAC control element.

19. An apparatus for a user equipment (UE), comprising:

a memory to store an activation/deactivation medium access control (MAC) control element; and

a baseband processor to;

identify the activation/deactivation MAC control element by a MAC protocol data unit (PDU) control element;

decode one or more octets of the activation/deactivation MAC control element comprising C fields, the number of first octets based on a number of serving cells (SCell) associated with the UE, each C field indicating an activation/deactivation status of a corresponding SCell; and

cause the UE to communicate with SCells corresponding to C fields with an activated status.

20. The apparatus of claim 19, wherein the one or more octets comprise:

one octet when there are less than eight SCells; and

four octets when there are eight or more SCells.

21. The apparatus of claim 20, wherein the one or more first octets comprise a single reserved bit.

22. The apparatus of claim 19, wherein Activation/Deactivation MAC control element is identified by a MAC PDU subheader with a logical channel identifier.

23. A machine readable storage medium including machine-readable instructions that, when executed by one or more processors of an evolved node B (eNB), cause the one or more processors to perform operations comprising:

generate an activation/deactivation medium access control (MAC) control element; and

encode a MAC protocol data unit (PDU), the MAC protocol data unit (PDU) comprising;

a subheader including a logical channel identifier to identify the activation/deactivation MAC control element; and

one or more octets comprising C fields, the number of octets based on a number of serving cells (SCell) associated with a UE, each C field indicating an activation/deactivation status of an SCell.

24. The machine readable storage medium of claim 23, wherein the one or more octets comprise:

one octet when there are less than eight SCells; and

four octets when there are eight or more SCells.

25. The machine readable storage medium of claim 24, wherein the one or more first octets comprise a single reserved bit.