SEMICONDUCTOR STRUCTURE AND METHOD FOR REVIEWING DEFECTS

• US 20180188185A1
• Filed: 01/02/2017
• Published: 07/05/2018
• Est. Priority Date: 01/02/2017
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Granted Patent: US 10,082,471 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00

Abstract

A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Claims

1. A semiconductor structure comprising:

a wafer comprising a plurality of viewing fields defined thereon;

a plurality of dies defined by a scribe line formed in each viewing field;

a plurality of mark patterns formed in the scribe line; and

a plurality of anchor patterns respectively formed in the review fields, the anchor patterns being different from the mark patterns.

2. The semiconductor structure according to claim 1, wherein the viewing fields are defined in a photolithography process and identified by a defect review apparatus.

3. The semiconductor structure according to claim 1, wherein the mark patterns comprise alignment mark patterns.

4. The semiconductor structure according to claim 1, wherein the anchor patterns are formed in the scribe line at a corner of the dies, respectively.

5. The semiconductor structure according to claim 4, wherein the anchor patterns are formed at the corner of the dies located at a corner of the viewing fields.

6. The semiconductor structure according to claim 4, wherein the anchor patterns are formed at the corner of the dies not located at a corner of the viewing fields.

7. The semiconductor structure according to claim 1, wherein the anchor patterns and mark patterns comprise different shapes.

8. The semiconductor structure according to claim 1, wherein the anchor patterns respectively comprise a plurality of sub-patterns arranged therein, and at least a programmed defect is formed in one of the sub-patterns.

9. The semiconductor structure according to claim 8, wherein the sub-patterns comprise semiconductor patterns, metal patterns, or insulating patterns.

10. The semiconductor structure according to claim 8, wherein the programmed defect comprises a gap defect, a short-end defect, or a bridge defect.

11. A method for reviewing defects, comprising:

receiving a semiconductor structure and sets of coordinates locating a plurality of defects formed thereon in a defect review apparatus;

identifying a plurality of viewing fields on the semiconductor structure and recognizing a plurality of origin points respectively in the viewing fields in the defect review apparatus, and each viewing field comprising a plurality of dies formed therein;

performing a first review step to review a plurality of anchor patterns in the viewing fields;

performing an offset correction after the first review step to re-locating the plurality of defects; and

performing a second review step to review the defects after the offset correction.

12. The method for reviewing the defects according to claim 11, wherein the sets of the coordinates are derived from a defect inspection apparatus.

13. The method for reviewing the defects according to claim 11, wherein the anchor patterns are formed at corners of the dies located at corners of the viewing fields.

14. The method for reviewing the defects according to claim 13, wherein the offset correction is performed to calculate a deviation between the anchor pattern and the origin point in the viewing fields.

15. The method for reviewing the defects according to claim 11, wherein the anchor patterns are formed at corners of the dies not located at corners of the viewing fields.

16. The method for reviewing the defects according to claim 15, wherein the offset correction is performed to calculate a deviation between the sets of coordinates and the anchor patterns.

17. The method for reviewing the defects according to claim 11, wherein the anchor patterns comprise a plurality of sub-patterns arranged within, and at least a programmed defect is formed in one of the sub-patterns.

18. The method for reviewing the defects according to claim 17, wherein the programmed defect comprises a gap defect, a short-end defect, or a bridge defect.