LINK POWER MANAGEMENT SCHEME BASED ON LINK'S PRIOR HISTORY

• US 20180188797A1
• Filed: 12/29/2016
• Published: 07/05/2018
• Est. Priority Date: 12/29/2016
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Application Number:
  US15/394,631
• Publication Number:
  US 20180188797A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus is described. The apparatus includes power management logic circuitry to implement a power management scheme for a link in which a prior history of the link'"'"'s idle time behavior is used to determine a first estimate of the link'"'"'s power consumption while idle in a higher power state and determine a second estimate of the link'"'"'s power consumption while idle in a lower power state. The first and second estimates are used to determine an idle time for the link at which the link is transitioned to the lower power state.

Claims

1. An apparatus, comprising;

power management logic circuitry to implement a power management scheme for a link in which a prior history of said link'"'"'s idle time behavior is used to determine a first estimate of said link'"'"'s power consumption while idle in a higher power state and determine a second estimate of said link'"'"'s power consumption while idle in a lower power state, and where said first and second estimates are used to determine an idle time for said link at which said link is transitioned to said lower power state.

2. The apparatus of claim 1 wherein said power management logic circuitry is to analyze multiple idle time candidates at which said link is transition-able from said higher power state to a said lower power state.

3. The apparatus of claim 2 wherein the following is reveal-able by said power management logic circuitry'"'"'s implementation of said power management scheme:

a) a first idle time when keeping said link in said higher power state is more power efficient than transitioning said link to said lower power state even though said link is idle; and

,

b) a second idle time when transitioning said link from said higher power state to said lower power state is more power efficient than keeping said link in said higher power state because said prior history indicates that said idle time is expected to be sufficiently extensive.

4. The apparatus of claim 1 wherein said second estimate includes an estimate of power consumption of waking said link.

5. The apparatus of claim 1 wherein said link is a PCIe link.

6. The apparatus of claim 1 wherein said link is a component in a multi-level system memory.

7. The apparatus of claim 1 wherein said power management logic circuitry includes counters, each counter of the counters to count a respective observed idle time of said prior history.

8. The apparatus of claim 1 wherein, if a comparison of said first and second estimates reveals that said link is expected to consume less power if said link remains in said higher power state than if said link were to transition to said lower power state at a first link idle time, said power management logic is to:

determine a third estimate of said link'"'"'s power consumption while idle in said higher power state for a second idle time that is longer than said first idle time and determine a fourth estimate of said link'"'"'s power consumption while idle in said lower power state for said second idle time.

9. The apparatus of claim 1 further comprising a computing system comprising a plurality of processing cores, a memory controller, said power management logic circuitry and said link.

10. An apparatus, comprising;

power management logic circuitry and power management program code stored on a computer readable storage medium, said power management logic circuitry and power management program code to implement a power management scheme for a link in which a prior history of said link'"'"'s idle time behavior is used to determine a first estimate of said link'"'"'s power consumption while idle in a higher power state and determine a second estimate of said link'"'"'s power consumption while idle in a lower power state, and where said first and second estimates are used to determine an idle time for said link at which said link is transitioned to said lower power state.

11. The apparatus of claim 10 wherein said power management logic circuitry and power management program code is to analyze multiple idle time candidates at which said link is transition-able from said higher power state to a said lower power state.

12. The apparatus of claim 11 wherein the following is reveal-able from said power management logic circuitry'"'"'s and power management program code'"'"'s implementation of said power management scheme:

a) a first idle time when keeping said link in said higher power state is more power efficient than transitioning said link to said lower power state even though said link is idle; and

,

b) a second idle time when transitioning said link from said higher power state to said lower power state is more power efficient than keeping said link in said higher power state because said prior history indicates that said idle time is expected to be sufficiently extensive.

13. The apparatus of claim 10 wherein said second estimate includes an estimate of power consumption of waking said link.

14. The apparatus of claim 10 wherein said link is a PCIe link.

15. The apparatus of claim 10 wherein said link is a component in a multi-level system memory.

16. The apparatus of claim 10 wherein said power management logic circuitry and/or power management program code includes counters, each counter of the counters to count a respective observed idle time of said prior history.

17. The apparatus of claim 10 wherein, if a comparison of said first and second estimates reveals that said link is expected to consume less power if said link remains in said higher power state than if said link were to transition to said lower power state at a first link idle time, said power management logic is to:

determine a third estimate of said link'"'"'s power consumption while idle in said higher power state for a second idle time that is longer than said first idle time and determine a fourth estimate of said link'"'"'s power consumption while idle in said lower power state for said second idle time.

18. The apparatus of claim 10 further comprising a computing system comprising a plurality of processing cores, a memory controller, said power management logic circuitry and power management program code and said link.

19. A computer readable storage medium containing program code that when processed by a computing system causes a method to be performed, comprising:

tracking a prior history of a link'"'"'s idle time behavior;

determining a first estimate of said link'"'"'s power consumption while idle in a higher power state;

determining a second estimate of said link'"'"'s power consumption while idle in a lower power state; and

,

using said first and second estimates to determine an idle time for said link at which said link is transitioned to said lower power state.

20. The computer readable storage medium of claim 19 further comprising analyzing multiple idle time candidates at which said link is transition-able from said higher power state to said lower power state.

21. The computer readable storage medium of claim 20 wherein said tracking further comprises maintaining counters for each of said multiple candidate idle times.

22. The computer readable storage medium of claim 19 wherein said second estimate includes an estimate of power consumption of waking said link.

23. The computer readable medium of claim 19 wherein said link is a component in a multi-level system memory.

24. The computer readable medium of claim 19 wherein said method further comprises comparing said first and second estimates and if said comparison reveals that said link is expected to consume less power if said link remains in said higher power state than if said link were to transition to said lower power state at a first link idle time, then, determining a third estimate of said link'"'"'s power consumption while idle in said higher power state for a second idle time that is longer than said first idle time and determining a fourth estimate of said link'"'"'s power consumption while idle in said lower power state for said second idle time.

25. A method, comprising;

tracking a prior history of a link'"'"'s idle time behavior;

determining a first estimate of said link'"'"'s power consumption while idle in a higher power state;

determining a second estimate of said link'"'"'s power consumption while idle in a lower power state; and

,

using said first and second estimates to determine an idle time for said link at which said link is transitioned to said lower power state.

26. The method of claim 25 further comprising analyzing multiple idle time candidates at which said link is transition-able from said higher power state to a said lower power state.

27. The method of claim 26 wherein said tracking further comprises maintaining counters for each of said multiple candidate idle times.

28. The method of claim 25 wherein said second estimate includes an estimate of power consumption of waking said link.

29. The method of claim 25 wherein said link is a component in a multi-level system memory.