RUNTIME ADDRESS DISAMBIGUATION IN ACCELERATION HARDWARE

• US 20180188983A1
• Filed: 12/30/2016
• Published: 07/05/2018
• Est. Priority Date: 12/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Granted Patent: US 10,474,375 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency

Abstract

An integrated circuit includes a processor to execute instructions and to interact with memory, and acceleration hardware, to execute a sub-program corresponding to instructions. A set of input queues includes a store address queue to receive, from the acceleration hardware, a first address of the memory, the first address associated with a store operation and a store data queue to receive, from the acceleration hardware, first data to be stored at the first address of the memory. The set of input queues also includes a completion queue to buffer response data for a load operation. A disambiguator circuit, coupled to the set of input queues and the memory, is to, responsive to determining the load operation, which succeeds the store operation, has an address conflict with the first address, copy the first data from the store data queue into the completion queue for the load operation.

Claims

1. An integrated circuit comprising:

a processor to execute instructions of a program and to interact with a memory;

acceleration hardware to execute a sub-program corresponding to the instructions;

a set of input queues coupled to the acceleration hardware and to the memory, the set of input queues comprising;

a store address queue to receive, from the acceleration hardware, a first address of the memory, the first address associated with a store operation; and

a store data queue to receive, from the acceleration hardware, first data to be stored at the first address of the memory;

a completion queue to buffer response data for a load operation; and

a disambiguator circuit coupled to the set of input queues and the completion queue, the disambiguator circuit to, responsive to determining the load operation that succeeds the store operation has an address conflict with the first address, copy the first data from the store data queue into the completion queue for the load operation.

2. The integrated circuit of claim 1, further comprising an operations queue coupled to the set of input queues, the operations queue to buffer address arguments for the store operation and the load operation, comprising:

a channel of the set of input queues at which to retrieve the first address for the store operation; and

a second channel of the set of input queues at which to retrieve the first address for the load operation.

3. The integrated circuit of claim 1, further comprising a scheduler circuit coupled to the set of input queues and to a memory interface, the scheduler circuit to:

schedule issuance of the store operation upon receipt of the first address; and

trigger generation of a dependency token to indicate, to the load operation, a dependency on the first data stored by the store operation.

4. The integrated circuit of claim 3, further comprising an execution circuit coupled to the scheduler circuit, to the set of input queues, and to the memory, the execution circuit to, upon detecting reception of the first data in the store data queue, issue the store operation to the memory with the dependency token, to store the first data at the first address.

5. The integrated circuit of claim 3, wherein the disambiguator circuit comprises a content-addressable memory (CAM), and the scheduler circuit is further to store an entry in the CAM, the entry comprising the first address and a pointer into the store data queue to a location at which to receive the first data.

6. The integrated circuit of claim 5, wherein the disambiguator circuit is further to stall in response to the CAM filling up with entries for scheduled store operations.

7. The integrated circuit of claim 5, wherein the scheduler circuit is further to, upon receipt of the first data in the store data queue, store the first data in the CAM in association with the entry, and wherein the disambiguator circuit is to retain the first data in a disambiguator queue of the disambiguator circuit, the first data to be forwarded to a subsequent memory operation that succeeds the load operation.

8. The integrated circuit of claim 5, wherein the set of input queues further comprises a load address queue to receive, from the acceleration hardware, the first address for the load operation, and wherein the scheduler circuit is further to:

detect, based on a search of the CAM, an address conflict between the load operation and the store operation;

retrieve the pointer from the CAM; and

annotate an indexed slot of the completion queue with the location in the pointer, to schedule issuance of the load operation upon receipt of the data at the location of the store data queue.

9. The integrated circuit of claim 1, wherein one of the set of input queues and the completion queue is a ring buffer.

10. A memory ordering circuit comprising:

a memory interface coupled to a memory, the memory to store data corresponding to instructions being executed for a program;

an operations queue coupled to the memory interface, the operations queue to buffer memory operations corresponding to the instructions;

a set of input queues coupled to the memory interface and to acceleration hardware, which is to execute a sub-program corresponding to the instructions, the set of input queues comprising;

a store address queue to receive, from the acceleration hardware, a first address of the memory for a store operation of the memory operations; and

a store data queue to receive, from the acceleration hardware, first data to be stored at the first address in completion of the store operation;

a disambiguator circuit coupled to the set of input queues, the disambiguator circuit including a disambiguator queue; and

an operations manager circuit coupled to the set of input queues and the disambiguator circuit, the operations manager circuit to;

schedule the store operation to issue to the memory upon receipt of the first address; and

store an entry in the disambiguator queue, the entry comprising the first address and a pointer into the store data queue to a location at which to receive the first data for the store operation.

11. The memory ordering circuit of claim 10, wherein the disambiguator circuit comprises one of a disambiguation content-addressable memory (CAM) or a counting Bloom filter.

12. The memory ordering circuit of claim 10, wherein the set of input queues further comprises a load address queue to receive a second address, from the acceleration hardware, for a succeeding load operation, wherein the operation manager is further to:

detect, based on a search requested of the disambiguator circuit, no address conflict between the store operation and the succeeding load operation; and

issue the load operation to the memory without waiting for completion of the store operation.

13. The memory ordering circuit of claim 10, wherein the set of input queues further comprises a load address queue to receive the first address, from the acceleration hardware, for a load operation that succeeds the store operation, further comprising:

a completion queue coupled to the operations manager circuit and to the memory, the completion queue to enqueue data received for completion of the load operation; and

a dependency queue coupled to the acceleration hardware and to receive, from the acceleration hardware, a dependency token associated with the first address for the load operation, the dependency token indicating a dependency on the first data to be stored by the store operation.

14. The memory ordering circuit of claim 13, wherein the completion queue is a ring buffer.

15. The memory ordering circuit of claim 13, wherein the operations manager circuit is further to:

detect, based on a search requested of the disambiguator circuit, an address conflict between the load operation and the store operation;

retrieve the pointer from the disambiguator queue; and

annotate an indexed slot of the completion queue with the location of the pointer, to schedule issuance of the load operation upon receipt of the data at the location in the store data queue.

16. The memory ordering circuit of claim 15, wherein the operations manager circuit is further to:

detect arrival of the first data at the location of the pointer into the store data queue; and

enqueue the data, from the location in the store data queue, into the indexed slot of the completion queue, to thereby complete data forwarding to the load operation.

17. The memory ordering circuit of claim 13, further comprising an operations queue coupled to the operations manager circuit and to the memory interface, the operations queue to buffer the load operation and the store operation, each of which comprise a memory argument containing an indication of whether to interact with the disambiguator circuit, wherein the operations manager circuit is further to, responsive to detecting the indication to access the disambiguator circuit:

direct the disambiguator circuit to store the entry for the store operation; and

check the disambiguator circuit for an address conflict between the store operation and the load operation.

18. The memory ordering circuit of claim 10, wherein the operations manager circuit is further to:

trigger generation of a dependency token to indicate, to a succeeding dependent memory operation, a dependency on the data stored by the store operation; and

in response to detecting receipt of the first data into the store data queue, issue a store command containing the dependency token directed to the first address in the memory.

19. A method comprising:

queuing memory operations in an operations queue of a memory ordering circuit, the memory operations directed towards a memory in association with acceleration hardware;

receiving, into a load address queue of a set of input queues, a load address received from the acceleration hardware for a load operation of the memory operations;

determining, by a disambiguator circuit, the load address matches a store address buffered in a store address queue for a store operation of the memory operations, the store operation preceding the load operation according to program order; and

marking, by the memory ordering circuit and in response to the determining, the load operation as a store forward with a pointer to a location, within a store data queue of the set of input queues, for reception of data to complete the store operation and the load operation.

20. The method of claim 19, further comprising:

scheduling the store operation to issue to the memory upon receipt of the store address; and

storing an entry in a disambiguator queue of the disambiguator circuit, the entry comprising the store address and the pointer.

21. The method of claim 20, further comprising:

storing the data in the disambiguator queue in association with the entry, in response to receiving the data into the store data queue; and

retaining the data, in the disambiguator queue, to be forwarded to a subsequent memory operation that succeeds the load operation.

22. The method of claim 20, further comprising, in response to receiving the data into the location of the store data queue:

copying the data, from the location in the store data queue, into an indexed slot of a completion queue for the load operation;

issuing the store operation to the memory to complete the store operation; and

sending the data, from the completion queue, to the acceleration hardware in response to the load operation.

23. The method of claim 22, further comprising retaining the data, in the store data queue, after completion of the store operation, to fulfill at least a second load operation.

24. The method of claim 22, further comprising:

receiving, in a dependency queue of the set of input queues, a dependency token associated with the load address buffered in the load address queue, the dependency token indicating dependency on the data stored by the store operation;

duplicating the dependency token for a subsequent memory operation that is dependent on the load operation; and

wherein the sending the data to the acceleration hardware further comprises sending the dependency token with the data to the acceleration hardware, to complete the load operation.