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MEMORY ORDERING IN ACCELERATION HARDWARE

  • US 20180188997A1
  • Filed: 12/30/2016
  • Published: 07/05/2018
  • Est. Priority Date: 12/30/2016
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a memory interface coupled to a memory, the memory to store data corresponding to instructions being executed for a program;

    an operations queue coupled to the memory interface, the operations queue to buffer memory operations corresponding to the instructions;

    acceleration hardware to execute a sub-program corresponding to the instructions;

    a set of input queues coupled to the acceleration hardware and to the memory interface, wherein the set of input queues are to receive, from the acceleration hardware;

    an address, of the memory, associated with a second memory operation of the memory operations; and

    a dependency token, associated with the address, that indicates a dependency on data generated by a first memory operation, of the memory operations, which precedes the second memory operation; and

    a scheduler circuit coupled to the memory interface, the operations queue, and the set of input queues, wherein the scheduler circuit is to schedule issuance of the second memory operation to the memory in response to receipt, by the set of input queues, of the dependency token and the address.

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