PROCESSORS, METHODS, AND SYSTEMS WITH A CONFIGURABLE SPATIAL ACCELERATOR

• US 20180189063A1
• Filed: 12/30/2016
• Published: 07/05/2018
• Est. Priority Date: 12/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Granted Patent: US 10,416,999 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 15/825 Dataflow computers
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

Claims

1. A processor comprising:

a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation;

a plurality of processing elements; and

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

2. The processor of claim 1, wherein a processing element of the plurality of processing elements is to stall execution when a backpressure signal from a downstream processing element indicates that storage in the downstream processing element is not available for an output of the processing element.

3. The processor of claim 2, further comprising a flow control path network to carry the backpressure signal according to the dataflow graph.

4. The processor of claim 1, wherein a dataflow token causes an output from a dataflow operator receiving the dataflow token to be sent to an input buffer of a particular processing element of the plurality of processing elements.

5. The processor of claim 1, wherein the second operation comprises a memory access and the plurality of processing elements comprises a memory-accessing dataflow operator that is not to perform the memory access until receiving a memory dependency token from a logically previous dataflow operator.

6. The processor of claim 1, wherein the plurality of processing elements comprises a first type of processing element and a second, different type of processing element.

7. A method comprising:

decoding an instruction with a decoder of a core of a processor into a decoded instruction;

executing the decoded instruction with an execution unit of the core of the processor to perform a first operation;

receiving an input of a dataflow graph comprising a plurality of nodes;

overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements; and

performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

8. The method of claim 7, further comprising stalling execution by a processing element of the plurality of processing elements when a backpressure signal from a downstream processing element indicates that storage in the downstream processing element is not available for an output of the processing element.

9. The method of claim 8, further comprising sending the backpressure signal on a flow control path network according to the dataflow graph.

10. The method of claim 7, wherein a dataflow token causes an output from a dataflow operator receiving the dataflow token to be sent to an input buffer of a particular processing element of the plurality of processing elements.

11. The method of claim 7, further comprising not performing a memory access until receiving a memory dependency token from a logically previous dataflow operator, wherein the second operation comprises the memory access and the plurality of processing elements comprises a memory-accessing dataflow operator.

12. The method of claim 7, further comprising providing a first type of processing element and a second, different type of processing element of the plurality of processing elements.

13. An apparatus comprising:

a data path network between a plurality of processing elements; and

a flow control path network between the plurality of processing elements, wherein the data path network and the flow control path network are to receive an input of a dataflow graph comprising a plurality of nodes, the dataflow graph is to be overlaid into the data path network, the flow control path network, and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

14. The apparatus of claim 13, wherein the flow control path network is to carry backpressure signals to a plurality of dataflow operators according to the dataflow graph.

15. The apparatus of claim 13, wherein a dataflow token sent on the data path network to a dataflow operator causes an output from the dataflow operator to be sent to an input buffer of a particular processing element of the plurality of processing elements on the data path network.

16. The apparatus of claim 13, wherein the data path network is a static, circuit-switched network to carry the respective, input operand set to each of the dataflow operators according to the dataflow graph.

17. The apparatus of claim 13, wherein the flow control path network is to transmit a backpressure signal according to the dataflow graph from a downstream processing element to indicate that storage in the downstream processing element is not available for an output of the processing element.

18. The apparatus of claim 13, wherein at least one data path of the data path network and at least one flow control path of the flow control path network form a channelized circuit with backpressure control.

19. A method comprising:

receiving an input of a dataflow graph comprising a plurality of nodes; and

overlaying the dataflow graph into a plurality of processing elements of a processor, a data path network between the plurality of processing elements, and a flow control path network between the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements.

20. The method of claim 19, further comprising carrying backpressure signals with the flow control path network to a plurality of dataflow operators according to the dataflow graph.

21. The method of claim 19, further comprising sending a dataflow token on the data path network to a dataflow operator to cause an output from the dataflow operator to be sent to an input buffer of a particular processing element of the plurality of processing elements on the data path network.

22. The method of claim 19, further comprising setting a plurality of switches of the data path network to carry the respective, input operand set to each of the dataflow operators according to the dataflow graph, wherein the data path network is a static, circuit-switched network.

23. The method of claim 19, further comprising transmitting a backpressure signal with the flow control path network according to the dataflow graph from a downstream processing element to indicate that storage in the downstream processing element is not available for an output of the processing element.

24. The method of claim 19, further comprising forming a channelized circuit with backpressure control with at least one data path of the data path network and at least one flow control path of the flow control path network.