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HETEROGENEOUS HARDWARE ACCELERATOR ARCHITECTURE FOR PROCESSING SPARSE MATRIX DATA WITH SKEWED NON-ZERO DISTRIBUTIONS

  • US 20180189239A1
  • Filed: 12/31/2016
  • Published: 07/05/2018
  • Est. Priority Date: 12/31/2016
  • Status: Active Grant
First Claim
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1. A method in a hardware processor for processing sparse matrix data having a skewed non-zero distribution comprising:

  • determining, by the hardware processor, that one or more computational tasks involving a matrix are to be performed;

    partitioning, by the hardware processor, the matrix into a first plurality of blocks and a second plurality of blocks, wherein the first plurality of blocks includes one or more sections of the matrix that are sparse, and wherein the second plurality of blocks includes another one or more sections of the matrix that are very- or hyper-sparse; and

    causing, by the hardware processor, one or more sparse tiles of the hardware processor to perform one or more matrix operations for the one or more computational tasks using the first plurality of blocks and further causing one or more very/hyper sparse tiles of the hardware processor to perform the one or more matrix operations for the one or more computational tasks using the second plurality of blocks.

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