DISPLAY DEVICE HAVING SHARED COLUMN LINES

• US 20180190195A1
• Filed: 03/01/2018
• Published: 07/05/2018
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Granted Patent: US 10,170,042 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0404 Matrix technologies
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2300/0866 by means of changes in the pixel supply voltage
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/30 using electroluminescent panels
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/325 the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78645 : with multiple gate
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 : the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals

Abstract

A display device having at least a plurality of pixel circuits, connected to signal lines to which data signals in accordance with luminance information are supplied, arranged in a matrix, wherein pixel circuits of odd number columns and even number columns adjacent sandwiching an axis in a column direction parallel to an arrangement direction of the signal lines have a mirror type circuit arrangement symmetric about the axis of the column direction, and there are lines different from the signal lines between signal lines of adjacent pixel circuits.

Claims

1. A display device comprising:

a plurality of pixel circuits arranged in a matrix, the matrix including columns of the pixel circuits extending along a column direction, and the columns of the pixel circuits including a first pair of columns and a second pair of columns,

a plurality of signal lines extending along the column direction and configured to supply data signals;

a plurality of first control lines extending along a row direction perpendicular to the column direction and configured to supply scan signals;

a plurality of precharge potential lines extending along the column direction; and

a plurality of power supply potential lines extending along the column direction,

wherein one of the power supply potential lines is shared by pixel circuits in the first pair of columns,

one of the precharge potential lines is shared by pixel circuits in the second pair of columns,

the one of the power supply potential lines is located between the first pair of columns, but none of the precharge potential lines are located between the first pair of columns, and

the one of the precharge potential lines is located between the second pair of columns, but none of the power supply potential lines are located between the second pair of columns.

2. A display device as set forth in claim 1,

wherein transistors of a first pixel circuit in one of the first pair of columns and transistors of a second pixel circuit in the other of the first pair of columns are arranged in a symmetrical manner with respect to an axis along the column direction.

3. A display device as set forth in to claim 2,

wherein transistors of a third pixel circuit in one of the second pair of columns and transistors of a fourth pixel circuit in the other of the second pair of columns are arranged in a symmetrical manner with respect to an axis along the column direction.

4. A display device as set forth in claim 1, wherein at least one of the pixel circuits comprises:

a sampling transistor configured to sample one of the data signals;

a capacitor configured to store a voltage based on the sampled data signal;

a light emitting element configured to emit light in accordance with the voltage stored in the capacitor;

a driving transistor configured to supply current to the light emitting element;

a potential supply transistor configured to supply a precharge potential voltage to a node of the capacitor.

5. A display device as set forth in claim 4, wherein a first current electrode of the potential supply transistor is connected directly to the capacitor.

6. A display device as set forth in claim 4, further comprising:

a plurality of second control lines, wherein a gate electrode of the sampling transistor is connected to one of the first control lines, and a gate electrode of the potential supply transistor is connected to one of the second control lines.

7. A display device as set forth in claim 4, wherein the second control lines extend along the row direction.

8. A display device as set forth in claim 4, wherein said at least one of the plurality of pixel circuits further comprises:

a first switch transistor connected between the driving transistor and the light emitting element, wherein one of the source and drain electrodes of the first switch transistor is connected to one of the source and drain electrodes of the driving transistor through a first node, and an other one of the source and drain electrodes of the first switch transistor is connected to the light emitting element;

a second switch transistor connected between one end of the capacitor and the first node, wherein one of the source and drain electrodes of the second switch transistor is connected to the capacitor and an other one of the source and drain electrodes of the second switch transistor is connected to the first node.

9. A display device as set forth in claim 4, wherein at least the driving transistor is configured as a p-channel TFT.

10. A display device as set forth in claim 8, wherein the sampling transistor, the driving transistor, the potential supply transistor, the first switch transistor and the second switch transistor are configured as p-channel TFTs.

11. A display device as set forth in claim 1, further comprising:

control circuitry configured to perform an offset cancellation function for each of the plurality of pixel circuits, whereby variation of luminance caused by differences in threshold voltages of drive transistors is canceled.

12. A display device as set forth in claim 11, wherein the control circuitry is configured to perform the offset cancellation function for those of the plurality of pixels that are connected to the one of the precharge lines simultaneously.

13. A display device as set forth in claim 1, wherein two ends of each of the power supply potential lines are all connected to each other by a current path other than the power supply potential lines so as to become common and made the same potential.

14. A display device as set forth in claim 1, wherein the display device is an organic electroluminescence image display device.

15. A display device comprising:

a plurality of pixel circuits arranged in a matrix having rows and columns, wherein the pixel circuits includes a plurality of pairs of the pixel circuits which are adjacent to each other in a row direction;

a plurality of signal lines extending along a column direction perpendicular to the row direction and configured to supply data signals;

a plurality of first control lines extending along the row direction and configured to supply scan signals;

a plurality of precharge potential lines extending along the column direction and arranged between adjacent columns of the pixel circuits;

a plurality of power supply potential lines extending along the column direction and arranged between adjacent columns of the pixel circuits,

the precharge potential lines and the power supply potential lines are disposed between columns of the plurality of pixel circuits such that no adjacent columns of the pixel circuits have both one of the precharge potential lines and one of the power supply potential lines disposed therebetween, and

each of the pixel circuits is connected to a corresponding one of the power supply potential lines and a corresponding one of the precharge potential lines.

16. A display device as set forth in claim 15,

wherein each of the pairs of the pixel circuits includes a first pixel circuit and a second pixel circuit, and transistors of the first pixel circuit and transistors of the second pixel circuit are arranged in a symmetrical manner with respect to an axis along the column direction.

17. A display device as set forth in claim 15, wherein either of the plurality of precharge potential lines or the plurality of power supply potential lines are arranged between every adjacent columns.

18. A display device as set forth in claim 15, wherein at least one of the pixel circuits comprises:

a sampling transistor configured to sample one of the data signals;

a capacitor configured to store a voltage based on the sampled data signal;

a light emitting element configured to emit light in accordance with the voltage stored in the capacitor;

a driving transistor configured to supply current to the light emitting element;

a potential supply transistor configured to supply a precharge potential voltage to a node of the capacitor.

19. A display device as set forth in claim 16, wherein a first current electrode of the potential supply transistor is connected directly to the capacitor.

20. A display device as set forth in claim 16, further comprising:

a plurality of second control lines extending along the row direction, wherein a gate electrode of the sampling transistor is connected to one of the first control lines, and a gate electrode of the potential supply transistor is connected to one of the second control lines.

21. A display device as set forth in claim 15, wherein two ends of each of the power supply potential lines are all connected to each other by a current path other than the power supply potential lines so as to become common and made the same potential.

22. A display device comprising:

a plurality of pixel circuits arranged in a matrix, the matrix including columns of the pixel circuits extending along a column direction,

a plurality of signal lines extending along the column direction and configured to supply data signals;

a plurality of first control lines extending along a row direction perpendicular to the column direction and configured to supply scan signals;

a plurality of precharge potential lines extending along the column direction; and

a plurality of power supply potential lines extending along the column direction,

wherein a specific one of the power supply potential lines is shared by pixel circuits in a first column of the pixel circuits and a second column of the pixel circuits, the second column being adjacent to the first column

a first one of the precharge potential lines is connected to the pixel circuits in the first columns,

a second one of the precharge potential lines different from the first one of the precharge potential lines is connected to the pixel circuits in the second columns,

the pixel circuits in the first columns are between the first one of the precharge potential lines and the specific one of the power supply potential lines, and

the pixel circuits in the second columns are between the second one of the precharge potential lines and the specific one of the power supply potential lines.

23. A display device as set forth in claim 22, wherein pixel circuits in a third column of the pixel circuits are connected to the second one of the precharge potential lines, and

the second one of the precharge potential lines are disposed between the pixel circuits in the third column and the pixel circuits in the second column.

24. A display device as set forth in claim 22, wherein the second column and the third column are adjacent to each other.