SHIFT REGISTER, GATE DRIVING CIRCUIT AND DISPLAY DEVICE
First Claim
1. A shift register comprising:
- a first inputting circuit,a second inputting circuit,an outputting circuit,a node controlling circuit,a potential hold circuit, andan output-noise reduction circuit,wherein the first inputting circuit is configured to, under control of an input signal terminal, provide a signal from a first reference signal terminal to a first node PU,wherein the second inputting circuit is configured to, under control of a resetting signal terminal, provide a signal from a second reference signal terminal to the first node PU,wherein the outputting circuit is configured to, under control of the first node PU, provide a first clock signal from a first clock signal terminal to a signal outputting terminal of the shift register, and the outputting circuit is further configured to, under control of a second node, provide a signal from a third reference signal terminal to the signal outputting terminal,wherein the potential hold circuit is configured to, under control of both the first node and a touch control terminal, provide a signal from the touch control terminal to the first node PU,wherein the output-noise reduction circuit is configured to, under control of the touch control terminal, provide the signal from the third reference signal terminal to the signal outputting terminal,wherein the node controlling circuit is configured to, under control of the first node, provide the signal from the third reference signal terminal to the second node,wherein the node controlling circuit is further configured to, under control of a second clock signal terminal, provide a second clock signal from the second clock signal terminal to the second node,wherein the node controlling circuit is further configured to, when the second node is in a floating state, hold a stable potential difference between the second node and the first clock signal terminal,wherein phases of the first clock signal and the second clock signal are opposite.
1 Assignment
0 Petitions
Accused Products
Abstract
A shift register, a gate driving circuit and a display device are disclosed. The shift register includes a first inputting circuit, a second inputting circuit, an outputting circuit, a node controlling circuit, a potential hold circuit and an output-noise reduction circuit. The first inputting circuit and the second inputting circuit are to implement inputting to the first node and resetting of the first node. The node control circuit controls potentials of the first node and the second node. The outputting circuit controls the signal of the signal outputting terminal under control of the first node and the second node. The potential hold circuit can continuously charge the first node within a touch control period. The output-noise reduction circuit can perform noise reduction for the signal outputting terminal in the touch control period.
31 Citations
20 Claims
-
1. A shift register comprising:
-
a first inputting circuit, a second inputting circuit, an outputting circuit, a node controlling circuit, a potential hold circuit, and an output-noise reduction circuit, wherein the first inputting circuit is configured to, under control of an input signal terminal, provide a signal from a first reference signal terminal to a first node PU, wherein the second inputting circuit is configured to, under control of a resetting signal terminal, provide a signal from a second reference signal terminal to the first node PU, wherein the outputting circuit is configured to, under control of the first node PU, provide a first clock signal from a first clock signal terminal to a signal outputting terminal of the shift register, and the outputting circuit is further configured to, under control of a second node, provide a signal from a third reference signal terminal to the signal outputting terminal, wherein the potential hold circuit is configured to, under control of both the first node and a touch control terminal, provide a signal from the touch control terminal to the first node PU, wherein the output-noise reduction circuit is configured to, under control of the touch control terminal, provide the signal from the third reference signal terminal to the signal outputting terminal, wherein the node controlling circuit is configured to, under control of the first node, provide the signal from the third reference signal terminal to the second node, wherein the node controlling circuit is further configured to, under control of a second clock signal terminal, provide a second clock signal from the second clock signal terminal to the second node, wherein the node controlling circuit is further configured to, when the second node is in a floating state, hold a stable potential difference between the second node and the first clock signal terminal, wherein phases of the first clock signal and the second clock signal are opposite. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification