SEMICONDUCTOR WAFER AND METHOD OF PROBE TESTING
1. A method of making a semiconductor device, comprising:
- providing a semiconductor wafer;
providing a wafer holder including a tape portion with an opening through the tape portion;
mounting the semiconductor wafer over the opening in the tape portion of the wafer holder; and
providing an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.
A semiconductor test system has a wafer holder with a tape portion and one or more openings through the tape portion. A semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test. A plurality of bumps can be formed on the semiconductor wafer. The semiconductor wafer can be a stacked semiconductor wafer. A conductive trace can be formed on the tape portion and the semiconductor wafer probe tested through the conductive trace. An active surface or non-active surface of the semiconductor wafer can be oriented toward the tape portion. The electrical connection to the semiconductor wafer through the opening in the tape portion can be a ground reference node. A conductive layer is formed over a non-active surface of the semiconductor wafer.
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Patent #US 20100019442A1
Current AssigneeRicoh Company Limited
Sponsoring EntityRicoh Company Limited
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Patent #US 20130076384A1
Current AssigneePowertech Technology Inc
Sponsoring EntityPowertech Technology Inc
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Patent #US 20140252641A1
Current AssigneeJCET Semiconductor Shaoxing Co. Ltd.
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- 1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer; providing a wafer holder including a tape portion with an opening through the tape portion; mounting the semiconductor wafer over the opening in the tape portion of the wafer holder; and providing an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.
- View Dependent Claims (2, 3, 4, 5, 6)
- 7. An apparatus for probe testing a semiconductor device, comprising:
a semiconductor wafer; and a wafer holder including a tape portion with an opening through the tape portion, wherein the semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.
- View Dependent Claims (8, 9, 10, 11, 12, 13)
- 14. An apparatus for probe testing a semiconductor device, comprising:
a semiconductor wafer; and a wafer holder including a tape portion; and a conductive trace formed on the tape portion, wherein the semiconductor wafer is mounted over the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the conductive layer during probe test.
- View Dependent Claims (15, 16, 17, 18, 19, 20)
The present application is a continuation-in-part of U.S. patent application Ser. No. 15/704,246, filed Sep. 14, 2017, which is a continuation of U.S. patent application Ser. No. 15/230,875, now U.S. Pat. No. 9,793,186, filed Aug. 8, 2016, which applications are incorporated herein by reference.
The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor wafer and method of probe testing.
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Semiconductor devices perform a wide range of functions such as analog and digital signal processing, sensors, transmitting and receiving electromagnetic signals, controlling electronic devices, power management, and audio/video signal processing. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, diodes, rectifiers, thyristors, and power metal-oxide-semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, application specific integrated circuits (ASIC), power conversion, standard logic, amplifiers, clock management, memory, interface circuits, and other signal processing circuits.
A semiconductor wafer includes a base substrate material and plurality of semiconductor die formed on an active surface of the wafer separated by a saw street. Many applications require the semiconductor die to be reduced in height or thickness to minimize the size of the semiconductor package. Testing and inspection of the semiconductor wafer is important for quality assurance and reliability. Testing typically involves contacting a surface of the semiconductor wafer with a test probe. Yet, for large thin semiconductor wafers, wafer test probing often leads to breakage or damage from probe pressure on the thin wafer surface, as well as wafer handling and wafer warpage. The thin semiconductor wafers are subject to warpage. A warped thin semiconductor wafer is difficult to test because the test probes may not make contact with the warped surface.
In some cases, wafer test probing is performed prior to wafer thinning because the large thin wafers, e.g., wafers with a diameter of 150-300 millimeters (mm), may be warped beyond the test probe contact tolerance, or because the thin wafer surface cannot handle the invasive nature of the test. Wafer testing prior to wafer thinning is incomplete because certain features that are added post-wafer thinning, e.g., back-side metal, are not present for the test. In addition, for MOSFETS or wafers with through silicon vias, the current flows through the silicon and out the backside of the thinned wafer, i.e., through the back metal. Testing such devices is impractical for full-thickness wafers. The thickness of the wafers also affects the electrical performance. A thicker T-MOSFET wafer has more resistance than a thin wafer since the current must pass through more silicon. Wafer testing and inspection before all features are present reduces quality assurance, and adds manufacturing cost because an untested die must be assembled before functionality can be confirmed.
The following describes one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements. While the figures are described in terms of the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, evaporation, or other suitable metal deposition process. Conductive layer 112 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium tungsten (TiW), or other suitable electrically conductive material. Conductive layer 112 operates as interconnect pads electrically connected to the circuits on active surface 110.
In other embodiments, semiconductor wafer 100 represents stacked semiconductor wafers, stacked semiconductor die on the wafer, silicon-on-insulator type wafers, stacked memory wafers, memory devices stacked on a ASIC wafer, stacked through silicon conductive vias (TSV) semiconductor wafers, or any other configuration of stacked wafers, stacked die on wafers, and stacked devices.
Semiconductor wafer 100 undergoes electrical testing and inspection as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 100. Software can be used in the automated optical analysis of semiconductor wafer 100. Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, metallurgical microscope, or optical microscope. Semiconductor wafer 100 is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, contamination, and discoloration.
The active and passive components within semiconductor die 104 undergo testing at the wafer-level for electrical performance and circuit function. Each semiconductor die 104 is tested for functionality and electrical parameters. The raised portion 190b of surface 190 of wafer probing chuck 194 makes electrical contact with conductive layer 172 through opening 186. A computer controlled test system 196 sends electrical test signals through wafer probing chuck 194 and raised portion 190b of surface 190, which extends through opening 186, to provide electrical stimuli to conductive layer 172. Alternatively, computer controlled test system 196 sends electrical test signals through conductive channels within wafer probing chuck 194 and raised portion 190b of surface 190 to provide electrical stimuli to conductive layer 172. Conductive layer 172 is coupled to circuits on active surface 110 through TSV or vertically formed semiconductor devices. Semiconductor die 104 responds to the electrical stimuli, which is measured by computer test system 196 and compared to an expected response to test functionality of the semiconductor die.
The testing of semiconductor wafer 100 from the back-side directly to conductive layer 172 is achieved through raised portion 190b of surface 190 of wafer probing chuck 194 extending through opening 186 in tape portion 182 of film frame 180. Many testing procedures can be accomplished with wafer probe contact of raised portion 190b to conductive layer 172. For example, the electrical tests may include circuit functionality, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, threshold current, leakage current, and operational parameters specific to the component type. The testing is conducted with the thinned semiconductor wafer 100 after wafer grinding. The thinned semiconductor wafer 100 remains flat and stable by nature of lower portion 190a and raised portion 190b of surface 190 of wafer probing chuck 194 held against conductive layer 172. The inspection and electrical testing of semiconductor wafer 100, after wafer thinning, enables semiconductor die 104, with a complete feature set that passes, to be designated as known good die for use in a semiconductor package.
Wafer level testing also encompasses advanced testing procedures, including curve tracing of semiconductor wafer 100 or other characterization of the device, to evaluate detailed electrical and thermal performance of the thin wafer or stacked wafer.
Semiconductor wafer 100 can also be tested from active surface 110, as shown in
The tape portion may have multiple openings to provide access to different areas of conductive layer 172. As noted above, conductive layer 172 is patterned into electrically common or electrically isolated portions according to the function of semiconductor die 104.
Semiconductor wafer 100 is then mounted to tape portion 212, as shown in
The multiple raised portions 190b of surface 190 of wafer probing chuck 194 make electrical contact with corresponding areas of conductive layer 172 through openings 216. A computer controlled test system 220 sends electrical test signals through wafer probing chuck 194 and raised portions 190b of surface 190, which extends through openings 216, to provide electrical stimuli to different areas of conductive layer 172. Semiconductor die 104 responds to the electrical stimuli, which is measured by computer test system 220 and compared to an expected response to test functionality of the semiconductor die.
In one embodiment, as shown in
Alternatively, wafer ring holder 222 with grip ring 224, as shown in
In another embodiment, semiconductor wafer 100 is mounted to tape portion 225 without openings 226 to avoid stretching, non-uniformity, or other distortion in the tape portion or openings, see
In another embodiment, similar to
The wafer ring holder and semiconductor wafer 100 are moved from wafer probing chuck 194 and the thinned semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool or plasma etch into individual semiconductor die 104. The individual semiconductor die 104 from the thinned semiconductor wafer 100 have been probe tested in the final configuration of the semiconductor die.
While one or more embodiments have been illustrated and described in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present disclosure.