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Three-Dimensional Vertical Multiple-Time-Programmable Memory with A Thin Memory Layer

  • US 20180190715A1
  • Filed: 03/03/2018
  • Published: 07/05/2018
  • Est. Priority Date: 04/16/2016
  • Status: Abandoned Application
First Claim
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1. A three-dimensional vertical multiple-time-programmable memory (3D-MTPV), comprising:

  • a semiconductor substrate comprising a substrate circuit;

    a plurality of vertically stacked horizontal address lines above said semiconductor circuit;

    a plurality of memory holes through said horizontal address lines;

    a memory layer of less than 100 nm thick on the sidewalls of said memory holes and in contact with said horizontal address lines;

    a plurality of vertical address lines in said memory holes and in contact with said memory layer;

    a plurality of MTP cells at the intersections of said horizontal and vertical address lines;

    wherein the largest value of the reverse bias (VR) on said MTP cells during read is substantially smaller than the smallest value of the forward bias (VF) on said MTP cells during read.

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