Three-Dimensional Vertical Multiple-Time-Programmable Memory with A Thin Memory Layer
First Claim
Patent Images
1. A three-dimensional vertical multiple-time-programmable memory (3D-MTPV), comprising:
- a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit;
a plurality of memory holes through said horizontal address lines;
a memory layer of less than 100 nm thick on the sidewalls of said memory holes and in contact with said horizontal address lines;
a plurality of vertical address lines in said memory holes and in contact with said memory layer;
a plurality of MTP cells at the intersections of said horizontal and vertical address lines;
wherein the largest value of the reverse bias (VR) on said MTP cells during read is substantially smaller than the smallest value of the forward bias (VF) on said MTP cells during read.
0 Assignments
0 Petitions
Accused Products
Abstract
The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTPV) with a thin memory layer. It comprises a plurality of vertically stacked horizontal address lines, at least a memory hole through the horizontal address lines, a memory layer and a vertical address line disposed in the memory hole. Because the thickness of the memory layer is less than 100 nm, the MTP cell is leaky. Sense amplifiers and a full-read mode are used to ensure a properly working 3D-MTPV.
13 Citations
20 Claims
-
1. A three-dimensional vertical multiple-time-programmable memory (3D-MTPV), comprising:
-
a semiconductor substrate comprising a substrate circuit; a plurality of vertically stacked horizontal address lines above said semiconductor circuit; a plurality of memory holes through said horizontal address lines; a memory layer of less than 100 nm thick on the sidewalls of said memory holes and in contact with said horizontal address lines; a plurality of vertical address lines in said memory holes and in contact with said memory layer; a plurality of MTP cells at the intersections of said horizontal and vertical address lines; wherein the largest value of the reverse bias (VR) on said MTP cells during read is substantially smaller than the smallest value of the forward bias (VF) on said MTP cells during read. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification