Three-Dimensional Vertical Multiple-Time-Programmable Memory Comprising No Separate Diode Layer

• US 20180190716A1
• Filed: 03/03/2018
• Published: 07/05/2018
• Est. Priority Date: 04/16/2016
• Status: Abandoned Application

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Application Number:
  US15/911,112
• Publication Number:
  US 20180190716A1
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTP_V) comprising no separate diode layer. It comprises a plurality of vertically stacked horizontal address lines, at least a memory hole through the horizontal address lines, a memory layer and a vertical address line disposed in the memory hole. The memory layer comprises a re-programmable layer but no separate diode layer. The memory layer is leaky, i.e. its reverse current is comparable to its forward current. Sense amplifiers and a full-read mode are used to ensure a properly working 3D-MTP_V.

Claims

1. A three-dimensional vertical multiple-time-programmable memory (3D-MTP_V), comprising:

a semiconductor substrate comprising a substrate circuit;

a plurality of vertically stacked horizontal address lines above said semiconductor circuit;

a plurality of memory holes through said horizontal address lines;

a memory layer on the sidewalls of said memory holes and in contact with said horizontal address lines;

a plurality of vertical address lines in said memory holes and in contact with said memory layer;

a plurality of MTP cells at the intersections of said horizontal and vertical address lines;

wherein said memory layer comprises a re-programmable layer but no separate diode layer.

2. The 3D-MTP_V according to claim 1, wherein the largest value of the reverse bias (V_R) on said MTP cells during read is substantially smaller than the smallest value of the forward bias (V_F) on said MTP cells during read.

3. The 3D-MTP_V according to claim 1, further comprising:

at least a bit line associated with a selected one of said MTP cells; and

at least a sense amplifier coupling to said bit line.

4. The 3D-MTP_V according to claim 3, wherein the threshold voltage (V_t) of said sense amplifier is substantially smaller than the read voltage (V_r).

5. The 3D-MTP_V according to claim 1, wherein:

said horizontal address lines comprise at least a first conductive material;

said memory layer comprises at least a non-conductive material; and

said vertical address lines comprise at least a second conductive material.

6. The 3D-MTP_V according to claim 5, wherein said memory layer comprises a re-programmable layer.

7. The 3D-MTP_V according to claim 6, wherein said re-programmable layer comprises a resistive RAM (RRAM) layer.

8. The 3D-MTP_V according to claim 6, wherein said re-programmable layer comprises a phase-change memory (PCM) layer.

9. The 3D-MTP_V according to claim 5, wherein said first and second conductive materials are different conductive materials.

10. The 3D-MTP_V according to claim 9, wherein said first conductive material is a doped semiconductor material, and said second conductive material is an oppositely-doped semiconductor material.

11. The 3D-MTP_V according to claim 9, wherein said first conductive material is a metallic material, and said second conductive material is a doped semiconductor material.

12. The 3D-MTP_V according to claim 9, wherein said first conductive material is a doped semiconductor material, and said second conductive material is a metallic material.

13. The 3D-MTP_V according to claim 9, wherein said first conductive material is a first metallic material, said second conductive material is a second metallic material, and said first and second metallic materials have different work functions.

14. The 3D-MTP_V according to claim 1, wherein said horizontal address lines have a first interface with said memory layer, said vertical address lines have a second interface with said memory layer, and said first and second interfaces are different interfaces.

15. The 3D-MTP_V according to claim 1, wherein the data stored in all MTP cells coupled to a selected one of said horizontal address lines are read out in a single read cycle.

16. The 3D-MTP_V according to claim 15, wherein both said horizontal address lines and said vertical address lines are pre-charged to an initial voltage (V_i) during a pre-charge phase of said read cycle.

17. The 3D-MTP_V according to claim 16, wherein said vertical address lines are floating during a read-out phase of said read cycle.

18. The 3D-MTP_V according to claim 1, further comprising an MTP string including all MTP cells coupled to a selected vertical address line.

19. The 3D-MTP_V according to claim 18, further comprising a vertical transistor coupled to said MTP string.

20. The 3D-MTP_V according to claim 19, wherein said vertical transistor is formed in a first portion of said memory hole, and said MTP string is formed in a second portion of said memory hole.