METHOD AND STRUCTURE FOR PROTECTING GATES DURING EPITAXIAL GROWTH

• US 20180190787A1
• Filed: 02/26/2018
• Published: 07/05/2018
• Est. Priority Date: 06/19/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Granted Patent: US 10,446,665 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.

Claims

1-5. -5. (canceled)

6. A semiconductor structure, comprising:

a semiconductor substrate;

a transistor gate disposed on the semiconductor substrate;

a lower inner spacer disposed adjacent to a lower portion of the transistor gate;

an upper inner spacer disposed adjacent to an upper portion of the transistor gate and in contact with the lower inner spacer; and

an outer spacer disposed adjacent to the lower inner spacer and the upper inner spacer.

7. The semiconductor structure of claim 6, wherein the transistor gate comprises polysilicon.

8. The semiconductor structure of claim 6, wherein the lower inner spacer comprises silicon oxide.

9. The semiconductor structure of claim 6, wherein the upper inner spacer comprises silicon nitride

10. The semiconductor structure of claim 6, wherein the upper inner spacer comprises silicon carbon nitride.

11. The semiconductor structure of claim 6, wherein the upper inner spacer comprises silicon oxycarbide.

12. The semiconductor structure of claim 6, wherein the outer spacer comprises silicon nitride.

13. The semiconductor structure of claim 12, further comprising:

a stressor cavity formed in the semiconductor substrate adjacent to the transistor gate; and

a stressor material disposed in the stressor cavity.

14. The semiconductor structure of claim 13, wherein the stressor material comprises silicon germanium.

15. The semiconductor structure of claim 13, wherein the stressor cavity comprises a sigma cavity.

16. A semiconductor structure, comprising:

a semiconductor substrate;

a first transistor gate and a second transistor gate disposed on the semiconductor substrate;

a full inner spacer disposed adjacent to the first transistor gate;

an outer spacer disposed adjacent to the full inner spacer;

a lower inner spacer disposed adjacent to a lower portion of the second transistor gate;

an upper inner spacer disposed adjacent to an upper portion of the second transistor gate and in contact with the lower inner spacer; and

an outer spacer disposed adjacent to the lower inner spacer and upper inner spacer of the second transistor gate.

17. The semiconductor structure of claim 16, wherein the lower inner spacer comprises silicon oxide.

18. The semiconductor structure of claim 16, wherein the upper inner spacer comprises silicon nitride

19. The semiconductor structure of claim 16, wherein the upper inner spacer comprises silicon carbon nitride.

20. The semiconductor structure of claim 16, wherein the upper inner spacer comprises silicon oxycarbide.