Devices Having a Semiconductor Material That Is Semimetal in Bulk and Methods of Forming the Same

• US 20180190799A1
• Filed: 02/27/2018
• Published: 07/05/2018
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Granted Patent: US 10,461,179 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/461 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1207 : combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1222 : with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/127 : with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 : characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 : including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 : in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Claims

1. A method comprising:

forming an isolation region in a substrate, wherein the isolation region is between a first and second region of the substrate, and wherein at least a portion of the isolation region is configured to extend from a top surface of the substrate;

forming a first highly doped source/drain contact region in the first region of the substrate and a second highly doped source/drain contact region in the second region of the substrate;

forming a first gate electrode over the first highly doped source/drain contact region;

forming a second gate electrode over the second highly doped source/drain contact region;

forming a first opening through the first gate electrode and to the first highly doped source/drain contact region;

forming a second opening through the second gate electrode and to the second highly doped source/drain contact region;

depositing a first bismuth-containing semiconductor material in the first opening to form a first bismuth-containing channel structure, the first bismuth-containing channel structure being connected to the first highly doped source/drain contact region;

depositing a second bismuth-containing semiconductor material in the second opening to form a second bismuth-containing channel structure, the second bismuth-containing channel structure being connected to the second highly doped source/drain contact region;

forming a third source/drain contact region over and connected to the first bismuth-containing channel structure;

forming a fourth source/drain contact region over and connected to the second bismuth-containing channel structure;

forming a dielectric layer over the third source/drain contact region and the fourth source/drain contact region; and

crystallizing the first and second bismuth-containing semiconductor materials, the crystallizing comprising performing an anneal.

2. The method of claim 1, wherein the first bismuth-containing semiconductor material is doped with an n-type dopant.

3. The method of claim 1, wherein the second bismuth-containing semiconductor material is doped with a p-type dopant.

4. The method of claim 1, wherein a cross section of the first bismuth-containing channel structure has a largest dimension 53 nm or less, and a cross section of the second bismuth-containing channel structure has a largest dimension 53 nm or less.

5. The method of claim 1 further comprising:

forming a first contact electrically coupled to the first highly doped source/drain contact region;

forming a second contact electrically coupled to the first gate electrode;

forming a third contact electrically coupled to the third source/drain contact region;

forming a fourth contact electrically coupled to the second highly doped source/drain contact region;

forming a fifth contact electrically coupled to the second gate electrode; and

forming a sixth contact electrically coupled to the fourth source/drain contact region.

6. The method of claim 1, wherein the forming the first and second highly doped source/drain contact regions comprises:

forming a first mask on the second region of the substrate;

implanting a first dopant in the first region of the substrate to form a first doped well;

implanting a second dopant in the first doped well to form a first doped region;

removing the first mask from the second region of the substrate;

forming a second mask on the first region of the substrate;

implanting a third dopant in the second region of the substrate to form a second doped well;

implanting a fourth dopant in the second doped well to form a second doped region; and

removing the second mask from the first region of the substrate.

7. The method of claim 6, wherein the first and fourth dopants are p-type dopants and wherein the second and third dopants are n-type dopants.

8. The method of claim 1, wherein, after cyrstallizing, the first bismuth-containing channel structure and the second bismuth-containing channel structure each comprise a monocrystalline bismuth-containing material.

9. The method of claim 1, wherein the forming a first and second highly doped source/drain contact regions comprises:

recessing the substrate in the first region and the second region;

forming a first mask on the second region of the substrate;

epitaxially growing a p-doped epitaxial layer on the substrate and in the first region of the substrate;

epitaxially growing an n+-doped epitaxial layer on the p-doped epitaxial layer and in the first region of the substrate;

removing the first mask from the second region of the substrate;

forming a second mask on the first region of the substrate;

epitaxially growing an n-doped epitaxial layer on the substrate and in the second region of the substrate;

epitaxially growing a p+-doped epitaxial layer on the n-doped epitaxial layer and in the second region of the substrate; and

removing the first mask from the second region of the substrate.

10. The method of claim 1, wherein the first and second bismuth-containing semiconductor materials comprise doped bismuth (Bi).

11. A method comprising:

forming an isolation region in a substrate, wherein the isolation region extends above an upper surface of the substrate;

forming a first source/drain region adjacent a first sidewall of the isolation region;

forming a first dielectric layer over the first source/drain region;

forming a conductive layer over the first dielectric layer;

forming a second dielectric layer over the conductive layer;

forming a first opening through the second dielectric layer, the conductive layer, and the first dielectric layer to the first source/drain region; and

forming a semiconductor material in the first opening.

12. The method of claim 11, wherein the semiconductor material extends over an upper surface of the second dielectric layer.

13. The method of claim 11, wherein the semiconductor material comprises a bismuth-containing material.

14. The method of claim 11, wherein forming the semiconductor material comprises forming a bismuth-containing material in an amorphous or polycrystalline state, and further comprising annealing, the annealing crystallizing the bismuth-containing material.

15. The method of claim 14, further comprising forming a third dielectric layer over the semiconductor material, wherein the annealing is performed after forming the third dielectric layer.

16. The method of claim 11, wherein forming the first source/drain region comprises epitaxially growing a semiconductor material over the substrate.

17. A method comprising:

forming a first source/drain region in a substrate;

forming a first dielectric layer over the first source/drain region;

forming a conductive layer over the first dielectric layer;

forming a second dielectric layer over the conductive layer;

forming a first opening through the second dielectric layer, the conductive layer, and the first dielectric layer to the first source/drain region;

forming a gate dielectric along sidewalls of the first opening;

forming a semiconductor material in the first opening, the semiconductor material having a channel region and a second source/drain region, the semiconductor material being amorphous or polycrystalline; and

crystallizing the semiconductor material by annealing.

18. The method of claim 17, further comprising forming a third dielectric layer over the semiconductor material, wherein the crystallizing is performed after forming the third dielectric layer.

19. The method of claim 17, wherein the semiconductor material comprises a bismuth-containing material.

20. The method of claim 17, wherein the first source/drain region comprises an epitaxially grown region.