INSULATED GATE BIPOLAR TRANSISTOR AND PREPARATION METHOD THEREFOR

• US 20180190805A1
• Filed: 06/22/2016
• Published: 07/05/2018
• Est. Priority Date: 11/10/2015
• Status: Active Grant

• Current Assignee: Zhuzhou CRRC Times Electric Co., Ltd. (CRRC Corp. Ltd.)
• Original Assignee: Zhuzhou CRRC Times Electric Co., Ltd. (CRRC Corp. Ltd.)
• Granted Patent: US 10,418,469 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/8222 Bipolar technology
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

Provided are an insulated gate bipolar transistor and a preparation method therefor. An auxiliary groove gate, namely a structure of an auxiliary groove, an auxiliary gate layer and the corresponding gate oxide layer, is arranged below an emitting metal electrode between a first common groove and a second common groove so as to provide a carrier pathway when the insulated gate bipolar transistor is turned off, so that not only the turn-off speed of the insulated gate bipolar transistor is increased, but also the reverse-biased safety operation area characteristic of the insulated gate bipolar transistor is improved, thus improving the performance of the insulated gate bipolar transistor.

Claims

1. An insulated gate bipolar transistor comprising at least one cell, wherein the cell comprises:

a drift region;

a base region located on a surface of the drift region;

a first primary trench, a second primary trench and an auxiliary trench located at a side of the base region away from the drift region, wherein the auxiliary trench is located between the first primary trench and the second primary trench, the first primary trench, the second primary trench and the auxiliary trench all extend to the drift region, a first primary gate layer is arranged in the first primary trench, a second primary gate layer is arranged in the second primary trench, an auxiliary gate layer is arranged in the auxiliary trench, and a first gate oxide layer is arranged between an inner wall of the first primary trench and the first primary gate layer, between an inner wall of the second primary trench and the second primary gate layer, and between an inner wall of the auxiliary trench and the auxiliary gate layer;

an emitter metal electrode and an auxiliary gate layer extraction electrode located between the first primary trench and the second primary trench and located at a side of the auxiliary gate layer away from the drift region, wherein the emitter metal electrode extends to the base region, and an auxiliary gate oxide layer is arranged between the emitter metal electrode and the auxiliary gate layer; and

a first source region located between the first primary trench and the emitter metal electrode and located at a side of the base region away from the drift region, and a second source region located between the second primary trench and the emitter metal electrode and located at a side of the base region away from the drift region, wherein neither the first source region nor the second source region is in contact with the auxiliary trench.

2. The insulated gate bipolar transistor according to claim 1, further comprising:

at least one first virtual trench located at a side of the base region away from the drift region and located at a side of the first primary trench away from the auxiliary trench;

a first virtual gate layer arranged in the first virtual trench; and

a second gate oxide layer arranged between an inner wall of the first virtual trench and the first virtual gate layer.

3. The insulated gate bipolar transistor according to claim 1, further comprising:

at least one second virtual trench located at a side of the base region away from the drift region and located at a side of the second primary trench away from the auxiliary trench;

a second virtual gate layer arranged in the second virtual trench; and

a third gate oxide layer arranged between an inner wall of the second virtual trench and the second virtual gate layer.

4. The insulated gate bipolar transistor according to claim 1, further comprising:

a well region located between the base region and the drift region.

5. The insulated gate bipolar transistor according to claim 1, wherein a distance between the first primary trench and the auxiliary trench is the same as a distance between the second primary trench and the auxiliary trench.

6. The insulated gate bipolar transistor according to claim 1, wherein a depth of the first primary trench extending to the drift region, a depth of the second primary trench extending to the drift region, and a depth of the auxiliary trench extending to the drift region are the same.

7. The insulated gate bipolar transistor according to claim 1, wherein a width of the first primary trench, a width of the second primary trench, and a width of the auxiliary trench are the same.

8. The insulated gate bipolar transistor according to claim 1, wherein the first primary gate layer, the second primary gate layer and the auxiliary gate layer are all polysilicon gate layers.

9. A method for fabricating an insulated gate bipolar transistor, comprising:

providing a substrate, wherein the substrate comprises a drift region and a base region located on a surface of the drift region;

preparing a first primary trench, a second primary trench and an auxiliary trench at a side of the base region away from the drift region, preparing a first gate oxide layer at inner walls of the first primary trench, the second primary trench and the auxiliary trench, filling the first primary trench with a first primary gate layer, filling the second primary trench with a second primary gate layer, and filling the auxiliary trench with an auxiliary gate layer, wherein the auxiliary trench is located between the first primary trench and the second primary trench, and the first primary trench, the second primary trench and the auxiliary trench all extend to the drift region;

preparing a first source region between the first primary trench and the auxiliary trench, and preparing a second source region between the second primary trench and the auxiliary trench;

preparing an emitter metal electrode window between the first source region and the second source region, preparing an auxiliary gate oxide layer on a surface of a side of the auxiliary gate layer away from the drift region, that is located at the emitter metal electrode window, preparing an emitter metal electrode inside the emitter metal electrode window, and preparing an auxiliary gate layer extraction electrode on a surface of a side of the auxiliary gate layer away from the drift region, that is located outside the emitter metal electrode window, wherein two side edges of the emitter metal electrode window are in contact with the first source region and the second source region respectively and extend to the base region.

10. The method for fabricating the insulated gate bipolar transistor according to claim 9, wherein when preparing an emitter metal electrode window between the first source region and the second source region, the method further comprises:

preparing an auxiliary gate layer extraction electrode window at a side of the auxiliary gate layer away from the drift region, that is located outside the emitter metal electrode window, wherein the auxiliary gate layer extraction electrode window covers the auxiliary trench and the auxiliary gate layer extraction electrode is prepared at the auxiliary gate layer extraction electrode window.