ARRAY SUBSTRATE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND DISPLAY DEVICE

• US 20180190812A1
• Filed: 12/14/2015
• Published: 07/05/2018
• Est. Priority Date: 11/09/2015
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Granted Patent: US 10,644,159 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 10/82 Electrodes
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 71/231 by etching of existing layers
• CPC Class Codes: H10K 71/30 Doping active layers, e.g. electron transporting layers

Abstract

Disclosed is an array substrate, a method for manufacturing the array substrate, and a display device. The array substrate includes: a plurality of pixel units arranged in an array, each pixel unit being provided with one thin film transistor including an active layer and a polymer film on array. The polymer film on array is formed with a first via hole, and the active layer is conductive in a region thereof corresponding to the first via hole, such that a pixel electrode located on the polymer film on array is electrically connected to the source through the first via hole.

Claims

1. An array substrate, comprising:

a plurality of pixel units arranged in an array, each pixel unit being provided with one thin film transistor including a source and a drain that are located in a same layer, and an active layer connecting and partially covering the source and the drain, and

a polymer film on array covering the active layer,

wherein the polymer film on array is formed with a first via hole, and the active layer is conductive in a region thereof corresponding to the first via hole, such that a pixel electrode located on the polymer film on array is electrically connected to the source through the first via hole.

2. The array substrate according to claim 1, wherein the region of the active layer corresponding to the first via hole is an n-type heavily doped region.

3. The array substrate according to claim 2, wherein the active layer is made of oxide semiconductor.

4. The array substrate according to claim 3, wherein the region of the active layer corresponding to the first via hole is enabled to be the n-type heavily doped region by treatment with plasma.

5. The array substrate according to claim 4, wherein the plasma is hydrogen ions.

6. The array substrate according to claim 1, wherein an insulation layer is formed between the active layer and the polymer film on array, and the insulation layer is formed with a second via hole, the first via hole being nested in the second via hole.

7. A display device, comprising an array substrate, which includes:

a plurality of pixel units arranged in an array, each pixel unit being provided with one thin film transistor having a source and a drain that are located in a same layer, and an active layer connecting and partially covering the source and the drain, and

a polymer film on array covering the active layer,

wherein the polymer film on array is formed with a first via hole, and the active layer is conductive in a region thereof corresponding to the first via hole, such that a pixel electrode located on the polymer film on array is electrically connected to the source through the first via hole.

8. A method for manufacturing an array substrate, comprising the steps of:

forming a drain and a source on a same layer through one and a same patterning procedure;

forming an active layer partially covering the drain and the source on the drain and the source;

forming a polymer film on array, which is provided with a first via hole to expose the active layer partially;

treating a region of the active layer corresponding to the first via hole, such that the region of the active layer is conductive; and

forming a pixel electrode, which is electrically connected to the source through the region of the active layer corresponding to the first via hole.

9. The method of according to claim 8, wherein the step of treating a region of the active layer corresponding to the first via hole, such that the region of the active layer is conductive includes:

enabling the region of the active layer corresponding to the first via hole to be an n-type heavily doped region by treatment with plasma, such that the region of the active layer is conductive.

10. The method according to claim 9, wherein the plasma is hydrogen ions.