METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE

• US 20180190817A1
• Filed: 12/29/2016
• Published: 07/05/2018
• Est. Priority Date: 12/29/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Granted Patent: US 10,014,409 B1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

Claims

1. A method of making a vertical FinFET device comprising:

forming a fin having a height (H) on a semiconductor substrate;

forming a well region in the substrate, where a lower end of the fin is in contact with the well region;

forming a bottom source/drain region in the substrate laterally adjacent to the well region and spaced away from the fin,

forming a main gate stack over at least one sidewall of the fin, the main gate stack extending laterally over the well region and the bottom source/drain region on at least one side of the fin, wherein the main gate stack comprises a main gate dielectric and a main gate conductor formed over the main gate dielectric; and

etching a portion of the main gate conductor over the bottom source/drain region to define a channel region between the main gate conductor and the fin and between the main gate conductor and the well region.

2. The method of claim 1, wherein the channel region comprises a horizontal component over the well region on the at least one side of the fin, and a vertical component over the sidewall of the fin on the at least one side of the fin, and a length of the horizontal component is greater than a length of the vertical component.

3. The method of claim 1, further comprising forming a secondary gate stack over a sidewall of the fin opposite to the main gate stack, wherein the secondary gate stack comprises a secondary gate dielectric and a secondary gate conductor formed over the secondary gate dielectric.

4. The method of claim 3, wherein the secondary gate dielectric is the same as the main gate dielectric.

5. The method of claim 1, further comprising forming a hard mask over a top surface of the fin prior to forming the main gate stack.

6. The method of claim 1, wherein the main gate dielectric comprises silicon dioxide, a high dielectric constant (high-k) layer or a combination thereof.

7. The method of claim 1, further comprising forming a top source/drain region in contact with an upper end of the fin opposite to the lower end.

8. The method of claim 1, wherein forming the well region comprises forming a patterned masking layer, ion implantation, and removal of the patterned masking layer.

9. The method of claim 1, wherein forming the bottom source/drain region comprises forming a patterned masking layer, ion implantation, and removal of the patterned masking layer.

10. A vertical FinFET device comprising:

a fin disposed on a semiconductor substrate, the fin having a lower end in contact with a well region disposed within the substrate;

a main gate stack comprising a main gate dielectric and main gate conductor disposed over at least one sidewall of the fin and extending laterally over a portion of the well region on at least one side of the fin;

a channel region between the main gate conductor and the fin and between the main gate conductor and the well region on the at least one side of the fin; and

a bottom source/drain region laterally adjacent to the well region on the at least one side of the fin, wherein the portion of the well region underlying the main gate stack is disposed between the bottom source/drain region and the well region in contact with the lower end of the fin.

11. The vertical FinFET device of claim 10, wherein a length of the channel region on the at least one side of the fin is greater than a height (H) of the fin.

12. The vertical FinFET device of claim 10, wherein the main gate dielectric disposed over the fin and extending laterally over the well region comprises a high dielectric constant (high-k) layer, and further comprises an inner dielectric layer disposed between the high-k layer and the at least one sidewall of the fin and between the high-k layer and the well region.

13. The vertical FinFET device of claim 12, wherein the inner dielectric layer comprises silicon dioxide.

14. The vertical FinFET device of claim 10, wherein the semiconductor substrate is a bulk silicon substrate or silicon-on-insulator substrate.

15. The vertical FinFET device of claim 10, wherein the well region is doped to a peak concentration between 1×

10¹⁶ and 1×

10¹⁹ atoms/cm³.

16. The vertical FinFET device of claim 10, wherein the bottom source/drain region is doped to a peak concentration between 5×

10¹⁹ and 1×

10²¹ atoms/cm³.

17. The vertical FinFET device of claim 10, further comprising a top source/drain region in contact with an upper end of the fin opposite to the lower end.

18. The vertical FinFET device of claim 10, further comprising a secondary gate stack over a sidewall of the fin opposite to the main gate stack, wherein the secondary gate stack comprises a secondary gate dielectric and a secondary gate conductor formed over the secondary gate dielectric.

19. The vertical FinFET device of claim 18, wherein the secondary gate dielectric is the same as the main gate dielectric.

20. The vertical FinFET device of claim 10, wherein the main gate stack is in direct contact with the portion of the well region.