WAFER LEVEL PACKAGE WITH INTEGRATED OR EMBEDDED ANTENNA

• US 20180191053A1
• Filed: 01/03/2018
• Published: 07/05/2018
• Est. Priority Date: 01/05/2017
• Status: Active Grant

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Granted Patent: US 10,461,399 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24101 Connecting bonding areas at the same height
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/25171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 15/02 : Refracting or diffracting devices, e.g. lens, prism

Abstract

A wafer level package with integrated antenna includes a contacting layer, a redistribution layer as well as a chip layer arranged between the contacting layer and the redistribution layer. An antenna is integrated in the redistribution layer. The antenna is shielded from the chip by means of a via, offset and provided with a reflector. Alternatively, the antenna can also be provided as antenna element in the chip layer.

Claims

1. Wafer level package with integrated antenna, comprising:

a contacting layer;

a redistribution layer with the integrated antenna;

a chip layer comprising at least one chip arranged between the contacting layer and the redistribution layer;

wherein the integrated antenna is laterally arranged in the redistribution layer such that a projection area of the integrated antenna is offset from or partly overlapping with a projection area of the at least one chip;

wherein the contacting layer comprises a reflector and/or the reflector is arranged on a side facing away from the antenna; and

wherein at least one shielding via is arranged between the at least one integrated antenna and the at least one chip, wherein the at least one shielding via is configured to establish shielding between the integrated antenna and the at least one chip.

2. Wafer level package according to claim 1, wherein the integrated antenna is implemented as antenna array or comprises an antenna array.

3. Wafer level package according to claim 1, wherein the chip layer comprises polymer material that is arranged beside the at least one chip.

4. Wafer level package according to claim 3, wherein at least one via projects through the polymer material such that the redistribution layer is contacted.

5. Wafer level package according to claim 1, wherein the at least one shielding via is formed as a series of shielding vias.

6. Wafer level package according to claim 1, wherein the chip is contacted on both sides.

7. Wafer level package according to claim 1, wherein a dielectric is arranged between the chip layer and the redistribution layer.

8. Wafer level package according to claim 1, wherein the dielectric is perforated at least in part of an area of the integrated antenna.

9. Wafer level package according to claim 3, wherein the polymer material comprises at least one perforation structure in the area of the integrated antenna.

10. Wafer level package according to claim 3, wherein the polymer material comprises a spacer at least in one part of the area of the antenna.

11. Wafer level package according to claim 1, wherein the reflector is arranged overlapping with the projection area of the integrated antenna.

18. Wafer level package according to claim 1, wherein the at least one chip comprises a temperature dissipator on a side facing away from the redistribution layer.

20. Wafer level package according to claim 1, wherein the wafer level package comprises a lens that is configured to cooperate with at least one integrated antenna.

23. Wafer level package arrangement with a wafer level package according to claim 1 as well as one or several further wafer level packages.

12. Method for manufacturing a wafer level package with integrated antenna, comprising:

providing a chip layer comprising at least one chip;

depositing a contacting layer onto the chip layer; and

depositing a redistribution layer on the chip layer such that the redistribution layer is arranged opposite to the contacting layer, wherein the redistribution layer comprises at least the antenna;

wherein the integrated antenna is arranged laterally in the redistribution layer such that a projection area of the integrated antenna is offset from or partly overlapping with the projection area of the at least one chip;

wherein the contacting layer comprises a reflector and/or the reflector is arranged on a side facing away from the antenna; and

wherein at least one shielding via is arranged between the at least one integrated antenna and the at least one chip, wherein the at least one shielding via is configured to provide shielding between the integrated antenna and the at least one chip.

13. Method according to claim 12 comprising the step of introducing one or several vias through the polymer material, such that the redistribution layer is contacted.

14. Wafer level package with integrated antenna, comprising:

a contacting layer;

a redistribution layer; and

a chip layer comprising at least one chip as well as the integrated antenna, wherein the antenna is configured as individual component, arranged between the contacting layer and the redistribution layer;

wherein a shielding via is arranged between the at least one chip and the antenna, which is configured to shield the chip and the antenna from one another.

15. Wafer level package according to claim 14, wherein the integrated antenna is electrically connected to the chip layer via the redistribution layer.

16. Wafer level package according to claim 14, wherein the chip layer comprises a polymer material.

17. Wafer level package according to claim 16, wherein the redistribution layer is connected to the contacting layer by means of a via.

19. Wafer level package according to claim 14, wherein the at least one chip comprises a temperature dissipator on a side facing away from the redistribution layer.

21. Wafer level package according to claim 14, wherein the wafer level package comprises a lens that is configured to cooperate with at least one integrated antenna.

24. Wafer level package arrangement with a wafer level package according to claim 14 as well as one or several further wafer level packages.

22. Method for manufacturing a wafer level package with integrated antenna, comprising:

providing at least one chip and at least one antenna element, wherein the antenna is configured as individual component;

combining the at least one chip and the at least one antenna element to a chip layer;

depositing a contacting layer on the chip layer; and

depositing a redistribution layer on the chip layer such that the redistribution layer is arranged opposite to the contacting layer,

arranging a shielding via between the at least one chip and the antenna, which is configured to shield the chip and the antenna from one another.