APPARATUSES, METHODS, AND SYSTEMS FOR CIRCUITRY USING SYNCHRONOUS RECTIFIERS

• US 20180191267A1
• Filed: 01/03/2017
• Published: 07/05/2018
• Est. Priority Date: 01/03/2017
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Application Number:
  US15/397,599
• Publication Number:
  US 20180191267A1
• Time in Patent Office: Days
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Embodiments include apparatuses, methods, and systems for an alternating current (AC) to direct current (DC) converter including a synchronous rectifier to convert an AC input signal to a DC output signal. The AC to DC converter may further include a feedback circuit coupled to an output terminal of the synchronous rectifier to sample the DC output signal and to generate a digital signal to represent a voltage of the DC output signal and a controller coupled to receive the digital signal from the feedback circuit. The controller may compare the digital signal to a threshold, and based on the comparison, control an adjustment of the voltage of the DC output signal. Additional embodiments may also be described.

Claims

1. An alternating current (AC) to direct current (DC) converter, comprising:

a synchronous rectifier to convert an AC input signal to a DC output signal;

a feedback circuit coupled to an output terminal of the synchronous rectifier to sample the DC output signal and to generate a digital signal to represent a voltage of the DC output signal;

a controller coupled to receive the digital signal from the feedback circuit and to compare the digital signal to a threshold, and based on the comparison, to produce a binary signal; and

a digital-to-analog converter (DAC) coupled to receive the binary signal from the controller and, based on the binary signal, to generate a DC voltage to be applied to a gate terminal of a transistor of the synchronous rectifier to adjust a DC bias voltage level of the transistor to control the voltage of the DC output signal.

2. The AC to DC converter of claim 1, wherein the synchronous rectifier includes a metal-oxide-semiconductor-field-effect-transistor (MOSFET)-based full wave rectifier.

3. The AC to DC converter of claim 1, wherein the feedback circuit comprises an analog-to-digital converter (ADC).

5. The AC to DC converter of claim 1, further comprising a voltage adjustment circuit coupled to receive the DC voltage from the DAC and to apply the DC voltage to the gate terminal of the transistor of the synchronous rectifier.

6. The AC to DC converter of claim 5, wherein the voltage adjustment circuit is to apply the DC voltage to the gate terminal of the transistor of the synchronous rectifier in addition to an internal AC signal of the synchronous rectifier.

7. The AC to DC converter of claim 1, wherein the synchronous rectifier comprises a first pair of N-channel metal-oxide-semiconductor (NMOS)-field-effect transistors and a second pair of P-channel metal-oxide-semiconductor (PMOS)-field-effect transistors and the adjustment of the voltage of the DC output signal includes an adjustment of gate operating voltages in the first pair of transistors and the second pair of transistors.

8. The AC to DC converter of claim 7, wherein the controller is to control an adjustment of the gate operating voltages by increasing a DC voltage level to be applied to gate terminals of the first pair of NMOS-field-effect transistors if the voltage of the DC output signal is below the threshold.

9. The AC to DC converter of claim 7, wherein the controller is to control the adjustment of the gate operating voltages by decreasing a DC voltage level to be applied to gate terminals of the second pair of PMOS-field-effect transistors if the voltage of the DC output signal is below the threshold.

4. (canceled)

10. A transistor-based rectifier stage, comprising:

a rectifier circuit to convert an alternating current (AC) input signal to a direct current (DC) output signal; and

a digital controller coupled to receive a digital value representing a sample voltage of the DC output signal from the rectifier circuit and to compare a voltage of the DC output signal with a threshold to determine an adjustment of gate operating voltages by determining a DC voltage to apply to a gate terminal of a transistor of the rectifier circuit to adjust a DC bias voltage level to control the voltage of the DC output signal.

11. The transistor-based rectifier stage of claim 10 wherein the digital controller is to control the DC bias voltage level of the rectifier circuit to adjust the voltage of the DC output signal by facilitating a current flow through the transistor.

12. The transistor-based rectifier stage of claim 11 wherein the digital controller is to receive an updated digital signal, wherein if the updated digital signal indicates a resulting decrease in the voltage of the DC output signal, the digital controller is to control the DC bias voltage level to discourage the current flow through the transistor to increase the voltage of the DC output signal.

13. The transistor-based rectifier stage of claim 10, further comprising a voltage generator circuit coupled to receive a digital signal from the digital controller and to generate a DC voltage in response to the digital signal.

14. The transistor-based rectifier stage of claim 13, further comprising a voltage adjustment circuit coupled to receive the DC voltage from the voltage generator circuit and to apply the DC voltage to the gate terminal to adjust the voltage of the DC output signal.

15. The transistor-based rectifier stage of claim 10, wherein the rectifier circuit comprises a first pair of N-channel metal-oxide-semiconductor (NMOS)-field-effect transistors and a second pair of P-channel metal-oxide-semiconductor (PMOS)-field-effect transistors coupled to rectify the AC input signal.

16. The transistor-based rectifier stage of claim 15, wherein the digital controller adjusts the DC output signal of the rectifier by controlling an increase in a DC voltage of gate operating voltages of the first pair of NMOS-field-effect transistors.

17. The transistor-based rectifier stage of claim 16, wherein the digital controller adjusts the DC output signal of the rectifier by controlling a decrease of a DC voltage of gate operating voltages of the second pair of PMOS-field-effect transistors.

18. A system, comprising:

one or more processors;

a memory coupled to the one or more processors; and

a rectifier stage including;

a rectifier circuit;

a microcontroller coupled to the rectifier circuit, wherein the microcontroller includes;

an analog-to-digital converter (ADC) coupled to an output terminal of the rectifier circuit to sample a DC output signal generated by the rectifier circuit and to generate a signal to represent a value of the DC output signal;

a controller coupled to receive the signal from the ADC and to compare the signal to a threshold, and based on the comparison, to control an adjustment of a voltage of the DC output signal; and

a digital-to-analog converter (DAC) coupled to the controller to receive an instruction from the controller to generate a DC voltage to be applied to a gate terminal of a transistor in the rectifier circuit to adjust a DC bias voltage level of the transistor and control the voltage of the DC output signal;

wherein the rectifier stage is coupled to supply the adjusted DC output signal to the one or more processors or the memory.

19. The system of claim 18, wherein the rectifier circuit comprises first, second, third, and fourth metal-oxide-semiconductor-field-effect-transistor (MOSFET) devices coupled to rectify an input AC signal.

20. The system of claim 18, wherein the rectifier circuit comprises a first rectifier circuit and wherein the system further comprises a second rectifier circuit coupled to an input terminal of the first rectifier circuit and including fifth, sixth, seventh, and eighth MOSFET devices.

21. The system of claim 18, wherein the system comprises a radio-frequency identification (RFID) tag.

22. An apparatus, comprising:

means for converting an alternating current (AC) input signal to a direct current (DC) output signal;

means for sensing the DC output signal and for generating a digital signal to represent a voltage of the DC output signal; and

means for comparing the digital signal to a threshold.

23. The apparatus of claim 22, wherein the means for comparing the digital signal to the threshold includes means for comparing the digital signal to a predetermined tolerance voltage.

24. The apparatus of claim 22, further comprising means for sending an electrical interrupt signal to interrupt the means for comparing if a movement of the apparatus is detected.

25. The apparatus of claim 24, further comprising means for detecting a movement of the apparatus.