INTELLIGENT PACKET AGGREGATION

• US 20180191642A1
• Filed: 12/30/2016
• Published: 07/05/2018
• Est. Priority Date: 12/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Granted Patent: US 10,362,149 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 47/22 Traffic shaping
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 47/625 for service slots or service orders
• CPC Class Codes: H04L 47/6275 based on priority
• CPC Class Codes: H04L 47/6295 using multiple queues, one for each individual QoS, connection, flow or priority
• CPC Class Codes: H04L 49/9005 using dynamic buffer space allocation
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/321 Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers

Abstract

Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets'"'"' characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.

Claims

1. A network interface device for implementing intelligent packet aggregation, the network interface device comprising:

a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets'"'"' characteristics; and

a coordinator circuit to;

interface with a processing element to determine a current operational state of the processing element;

select a queue from the plurality of queues based on the current operational state of the processing element; and

forward a number of packets from the selected queue to the processing element.

2. The device of claim 1, wherein the processing element comprises a virtual machine.

3. The device of claim 1, wherein the processing element comprises a field-programmable gate array (FPGA) program.

4. The device of claim 1, wherein the packet parser includes a TCP offload engine to inspect the packets.

5. The device of claim 1, wherein the packet parser is to:

attempt to identify a queue of the plurality of queues that corresponds to a particular packet;

allocate a new queue when the identification fails; and

store the particular packet in the new queue.

6. The device of claim 1, wherein the current operational state of the processing element comprises a current operating thread.

7. The device of claim 1, wherein the current operational state of the processing element comprises a current operating process.

8. The device of claim 1, wherein the current operational state of the processing element comprises a current operating virtual machine.

9. The device of claim 1, wherein the current operational state of the processing element comprises a current FPGA configuration.

10. The device of claim 1, wherein to select the queue from the plurality of queues, the coordinator circuit is to:

determine a current priority associated a set of queues of the plurality of queues; and

select a queue with a highest priority from the set of queues.

11. The device of claim 10, wherein the current priority of a queue is increased when the current operational state indicates that the processing element is able to process packets stored in the queue.

12. The device of claim 10, wherein the current priority of a queue is decreased when the current operational state indicates that the processing element is unable to process packets stored in the queue.

13. The device of claim 1, wherein to forward the number of packets from the selected queue to the processing element, the coordinator circuit is to enforce a traffic regulation policy while forwarding the packets.

14. A method of implementing intelligent packet aggregation, the method comprising:

receiving, at a packet parser, a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets'"'"' characteristics;

interfacing with a processing element to determine a current operational state of the processing element;

selecting a queue from the plurality of queues based on the current operational state of the processing element; and

forwarding a number of packets from the selected queue to the processing element.

15. The method of claim 14, wherein the packet parser includes a TCP offload engine to inspect the packets.

16. The method of claim 14, further comprising:

attempting to identify a queue of the plurality of queues that corresponds to a particular packet;

allocating a new queue when the identification fails; and

storing the particular packet in the new queue.

17. The method of claim 14, wherein the current operational state of the processing element comprises a current operating thread.

18. The method of claim 14, wherein the current operational state of the processing element comprises a current operating process.

19. The method of claim 14, wherein the current operational state of the processing element comprises a current operating virtual machine.

20. The method of claim 14, wherein the current operational state of the processing element comprises a current FPGA configuration.

21. The method of claim 14, wherein selecting the queue from the plurality of queues comprises:

determining a current priority associated a set of queues of the plurality of queues; and

selecting a queue with a highest priority from the set of queues.

22. The method of claim 21, wherein the current priority of a queue is increased when the current operational state indicates that the processing element is able to process packets stored in the queue.

23. The method of claim 21, wherein the current priority of a queue is decreased when the current operational state indicates that the processing element is unable to process packets stored in the queue.

24. At least one machine-readable medium including instructions for implementing intelligent packet aggregation, which when executed by a machine, cause the machine to:

receive, at a packet parser, a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets'"'"' characteristics;

interface with a processing element to determine a current operational state of the processing element;

select a queue from the plurality of queues based on the current operational state of the processing element; and

forward a number of packets from the selected queue to the processing element.

25. The medium of claim 24, further comprising instructions to:

attempt to identify a queue of the plurality of queues that corresponds to a particular packet;

allocate a new queue when the identification fails; and

store the particular packet in the new queue.