MODULAR OFFLOADING FOR COMPUTATIONALLY INTENSIVE TASKS

• US 20180196698A1
• Filed: 03/05/2018
• Published: 07/12/2018
• Est. Priority Date: 02/18/2015
• Status: Active Application

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Mak, Hong Beng
• Application Number:
  US15/912,307
• Publication Number:
  US 20180196698A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups

Abstract

Systems and methods are provided for configuring a programmable integrated circuit device. A hard processor region of the programmable integrated circuit device includes a processor that identifies one or more tasks for assigning to an offload region of the programmable integrated circuit. The processor in the hard processor region transmits an instruction to the offload region. The plurality of offload nodes in the offload region are configured to perform the one or more tasks.

Claims

1. A method of configuring a programmable integrated circuit device, the method comprising:

identifying, by a processor in a hard processor region of the programmable integrated circuit device, one or more tasks for assigning to an offload region of the programmable integrated circuit device;

transmitting, by the processor in the hard processor region, an instruction to the offload region;

configuring a plurality of offload nodes in the offload region to perform the one or more tasks.