DIGITAL-DRIVE PULSE-WIDTH-MODULATED OUTPUT SYSTEM

• US 20180197471A1
• Filed: 01/26/2017
• Published: 07/12/2018
• Est. Priority Date: 01/10/2017
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Rotzoll, Robert R., Cok, Ronald S.
• Granted Patent: US 10,832,609 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes

Abstract

An active-matrix digital-drive display system includes an array of pixels. Each pixel has an output device, a serial digital memory responsive to a load timing signal for receiving and storing a multi-bit digital pixel value during an uninterrupted load time period, and a drive circuit responsive to a pulse-width-modulation (PWM) timing signal and to the multi-bit digital pixel value to drive the output device during an uninterrupted output time period. A controller external to the array of pixels provides to each pixel the load timing signal and the multi-bit digital pixel value during the load time period and the PWM timing signal during the output time period. The PWM timing signal has multiple different PWM time periods that are sequentially provided at different times to the pixels. Each PWM time period has a different temporal length corresponding to a bit of the multi-bit digital pixel value.

Claims

1. An active-matrix digital-drive display system, comprising:

an array of pixels arranged in rows and columns, each pixel having an output device, a serial digital memory responsive to a load timing signal for receiving and storing a multi-bit digital pixel value during an uninterrupted load time period, and a drive circuit responsive to a pulse-width-modulation (PWM) timing signal and to the multi-bit digital pixel value to drive the output device during an uninterrupted output time period subsequent to the load time period; and

a controller external to the array of pixels providing to each pixel the load timing signal and the multi-bit digital pixel value during the load time period and the PWM timing signal during the output time period;

wherein

the PWM timing signal has multiple different PWM time periods that are sequentially provided at different times to the pixels, each PWM time period having a different temporal length corresponding to a different bit of the multi-bit digital pixel value.

2. The digital-drive display system of claim 1, wherein the one or more output devices are a light-emitter, light-controller, a light-emitting diode, or an inorganic light-emitting diode that emits light.

3. The digital-drive display system of claim 1, wherein the serial digital memory and drive circuit of each pixel is provided in a single pixel-control integrated circuit having a separate, independent, and distinct substrate and a broken or separated tether and the output device is provided in an integrated circuit having a substrate separate, independent, and distinct from the pixel-control integrated circuit and a broken or separated tether.

4. The digital-drive display system of claim 1, wherein the serial digital memory stores three independent multi-bit digital pixel values and each pixel has three output devices and three drive circuits responsive to the same PWM timing signal at the same time, each of the three output devices responsive to a different one of the three multi-bit digital pixel values stored in the serial digital memory.

5. The digital-drive display system of claim 4, wherein the serial digital memory and the three drive circuits of each pixel are provided in a single pixel-control integrated circuit having a separate, independent, and distinct substrate and a broken or separated tether and the output devices are each provided in an integrated circuit having a substrate separate, independent, and distinct from the pixel-control integrated circuit and a broken or separated tether.

6. The digital-drive display system of claim 1, comprising a display substrate and wherein the pixels are spatially distributed over the display substrate and are separated by a distance greater than the distance between any of the output device, serial digital memory, and drive circuit of a pixel.

7. The digital-drive display system of claim 1, wherein at least one of the different PWM time periods has a temporal length that is unequal to a power of two times the shortest PWM time period.

8. The digital-drive display system of claim 1, wherein the controller provides a load timing signal and a PWM timing signal to all of the pixels in a row.

10. The digital-drive display system of claim 1, wherein the controller applies PWM timing signals to rows of pixels, and wherein the PWM time periods provided to at least one row of pixels are ordered differently from or are temporally out of phase with the PWM time periods of another, different row of pixels or wherein the controller applies PWM timing signals to columns of pixels, and wherein the PWM time periods provided to at least one column of pixels are ordered differently from or are temporally out of phase with the PWM time periods of another, different column of pixels.

11. The digital-drive display system of claim 1, wherein the pixels are controlled by only two control wires, exclusive of any power or ground connections.

12. The digital-drive display system of claim 1, wherein the output time period is greater than or equal to twice the duration of the PWM timing signal.

13. The digital-drive display system of claim 1, wherein each pixel comprises a separate, independent, and distinct pixel substrate on which each of the output devices is individually mounted and a pixel-control integrated circuit including the serial digital memory and drive circuit is mounted.

9. The digital-drive display system of claim 9, wherein the controller comprises serially connected row controllers having separate, independent and distinct substrates each connected to a row of pixels or wherein the controller comprises serially connected column drivers having separate, independent and distinct substrates each connected to a column of pixels.

15. An active-matrix digital PWM display having a display area, comprising:

an array of pixels forming rows and columns disposed in the display area, each pixel having an output device, a serial digital memory responsive to a load timing signal for receiving and storing a multi-bit digital pixel value during an uninterrupted load time period, and a drive circuit responsive to a pulse-width-modulation (PWM) timing signal and to the multi-bit digital pixel value to drive the output device during an uninterrupted output time period subsequent to the load time period;

an array of row-select lines, each row-select line connected in common to a different row of pixels;

an array of column-data lines connected in common to each column of pixels; and

an array of serially connected row controllers having separate, independent and distinct substrates external to the array of pixels, each row controller connected to a row of pixels providing in common to each pixel in the row the load timing signal during the load time period and the PWM timing signal during the output time period;

wherein

the PWM timing signal has multiple different PWM time periods that are sequentially provided at different times to the pixels, each timing period having a different temporal length corresponding to a different bit of the multi-bit digital pixel value.

14. The digital-drive display system of claim 16, wherein the pixel substrate has a broken or separated tether.

16. The digital PWM display of claim 15, comprising column drivers having separate, independent and distinct substrates, each column driver connected to a column-data line, the column drivers sequentially providing the bits of the multi-bit digital pixel values, and the row controllers and the column drivers each having a broken or separated tether.

17. The digital PWM display of claim 16, wherein the row controller provides a load timing signal to the row-select lines in conjunction with the column driver sequentially providing the bits of the multi-bit digital pixel values on the column-data lines.

18. The digital PWM display of claim 17, wherein a first row controller provides a load timing signal to a first row of pixels at the same time as a second row controller different from the first row controller provides a PWM timing signal to a second row of pixels different from the first row.

19. The digital PWM display of claim 17, wherein the row controller provides two or more output time periods for every load time period.

20. A method of controlling an active-matrix digital PWM display according to claim 15, comprising:

providing an array of multi-bit digital pixel values having rows and columns of multi-bit digital pixel values corresponding to the rows and columns of pixels in the array of pixels;

providing a load signal on the row-select line of a row of pixels with the row controller connected to the row-select line and, at the same time, sequentially providing the bits of the corresponding multi-bit digital pixel values to the column-data lines during a load time period; and

subsequent to the load time period, providing a PWM timing signal one or more times to the row-select line during the output time period.

21. (canceled)

22. An active-matrix digital-drive system, comprising:

an array of elements arranged in rows and columns, each element having an output device, a serial digital memory responsive to a load timing signal for receiving and storing a multi-bit digital element value during an uninterrupted load time period, and a drive circuit responsive to a pulse-width-modulation (PWM) timing signal and to the multi-bit digital element value to drive the output device during an uninterrupted output time period subsequent to the load time period; and

a controller external to the array of elements providing to each element the load timing signal and the multi-bit digital elements value during the load time period and the PWM timing signal during the output time period;

wherein

the PWM timing signal has multiple different PWM time periods that are sequentially provided at different times to the elements, each PWM time period having a different temporal length corresponding to a different bit of the multi-bit digital element value.

23. An active-matrix digital-drive pixel controller, comprising:

a pixel substrate;

a pixel circuit formed in or on the pixel substrate, the pixel circuit comprising;

an output device,

a serial digital memory responsive to a load timing signal for receiving and storing a multi-bit digital pixel value during an uninterrupted load time period, and

a drive circuit responsive to a pulse-width-modulation (PWM) timing signal and to the multi-bit digital pixel value to drive the output device during an uninterrupted output time period subsequent to the load time period;

wherein the pixel controller is responsive to the load timing signal and the multi-bit digital pixel value during the load time period and the PWM timing signal during the output time period; and

wherein the PWM timing signal has multiple different PWM time periods that are sequentially provided at different times to the pixels, each PWM time period having a different temporal length corresponding to a different bit of the multi-bit digital pixel value.