AUTOMATIC BIAS CONTROLLER FOR A PULSED POWER AMPLIFIER

• US 20180198414A1
• Filed: 03/06/2018
• Published: 07/12/2018
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Teledyne FLIR LLC (Teledyne Technologies Incorporated)
• Original Assignee: FLIR Systems, Inc. (Teledyne Technologies Incorporated)
• Inventors: Jales, Richard
• Granted Patent: US 10,454,425 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/30 Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in differential amplifiers H03F3/45479
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/462 the current being sensed
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence

Abstract

Systems and methods for automatically controlling the bias in a pulsed power amplifier include components for measuring the current in an amplifier, comparing the measured value with the desired value, modifying the bias, and controlling the bias applied to the power amplifier. A measurement circuit converts the measured current to a voltage, and a comparator compares a measured voltage with a reference voltage to continuously indicate whether the amplifier current is less than a desired quiescent value. A circuit controls the level of the gate-bias (Vg) during a pulse, such as with a pulse width modulator. The measurement of the amplifier current is registered after the bias is enabled, but before the signal pulse. Drive control logic implements a control algorithm for adjusting the gate value in between pulses and in time to be used for the next pulse.

Claims

1. A system comprising:

a power amplifier characterized by an associated quiescent current value;

a measurement circuit configured to measure a current supplied to the power amplifier;

a comparison circuit configured to compare the measured current to the quiescent current value; and

a bias controller coupled to the comparison circuit, the bias controller configured to adjust a bias signal provided to the power amplifier based on the comparison, wherein the bias signal is adjusted between pulses for use with a next pulse.

2. The system of claim 1, wherein the measurement circuit comprises:

a current transformer coupled to the power amplifier supply, the current transformer configured to convert the measured current to a measured voltage.

3. The system of claim 2, wherein the comparison circuit comprises:

a reference signal generator providing a reference signal having the quiescent current value; and

a comparator coupled to the measurement circuit to receive the measured voltage, wherein the comparator outputs a logic signal (ID_LOW) indicating whether the measured voltage is less than the quiescent current value.

4. The system of claim 1, wherein the bias controller comprises:

a pulse width modulator configured to produce a pulse width modulated signal (PA_PWM) and supply the PA_PWM to the power amplifier; and

power amplifier drive control logic configured to adjust the PA_PWM based on the output of the comparison circuit.

5. The system of claim 4, wherein the power amplifier drive control logic is further configured to increment PA_PWM if ID_LOW is true, and decrement PA_PWM if ID_LOW is false.

6. The system of claim 1, wherein the bias controller comprises a field programmable gate array.

7. The system of claim 1, further comprising:

a waveform generator providing a pulsed waveform signal to the power amplifier; and

a transmitter configured to transmit the amplified pulsed waveform signal.

8. The system of claim 7, wherein the transmitted signal is a remote sensor signal.

9. The system of claim 8, wherein the remove sensor signal is at least one of a radar signal or a sonar signal.

10. A method comprising:

determining a quiescent current value of a power amplifier;

measuring a current supplied to the power amplifier;

comparing the measured current to the quiescent current value; and

adjusting a bias of the power amplifier using the comparison.

11. The method of claim 10, wherein adjusting the bias comprises:

controlling the bias applied to the power amplifier using a control circuit for timing a gate pulse provided to the power amplifier.

12. The method of claim 10, wherein measuring the current comprises:

converting the current received from a power amplifier supply to a measured voltage using a current transformer.

13. The method of claim 12, wherein comparing the measured current to the quiescent current value comprises:

providing a reference signal having the quiescent current value;

receiving the measured voltage; and

setting a value of a logic signal (ID_LOW) to indicate whether the measured voltage is less than the quiescent current value.

14. The method of claim 10, wherein adjusting the bias comprises:

producing a pulse width modulated signal (PA_PWM) for supply to the power amplifier; and

adjusting the PA_PWM based on the comparison.

15. The method of claim 14, wherein adjusting the PA_PWM comprises:

incrementing PA_PWM by one if ID_LOW is true; and

decrementing PA_PWM by one if ID_LOW is false.

16. A system comprising:

a power amplifier having an associated quiescent current value;

a measurement circuit configured to measure a current supplied to the power amplifier;

a comparison circuit configured to compare the measured current to the quiescent current value;

digital circuitry coupled to the comparison circuit and configured to adjust a bias applied to the power amplifier using the output of the comparison circuit; and

a gate control circuit for providing a bias adjusted drive signal to the power amplifier.

17. The system of claim 16, wherein the digital circuitry comprises:

a pulse width modulator configured to produce a pulse width modulated signal (PA_PWM); and

power amplifier drive control logic configured to adjust the PA_PWM using the output of the comparison circuit;

wherein the PA_PWM is adjusted between pulses and in time for use with a next pulse.

18. The system of claim 17, wherein the power amplifier drive control logic is further configured to increment the PA_PWM by one if ID_LOW is true, and decrement the PA_PWM by one if ID_LOW is false.

19. The system of claim 17, wherein the digital circuitry further comprises:

a microcontroller for controlling the operation of the digital circuitry, including execution of the power amplifier drive control logic.

20. The system of claim 17, further comprising:

a low pass filter coupled to the digital circuitry to receive the PA_PWM; and

a power amplifier gate control circuit coupled to the output of the low pass filter and configured to provide a power amplifier gate drive signal to the power amplifier during a pulse.