GLITCH CHARACTERIZATION IN DIGITAL-TO-ANALOG CONVERSION

• US 20180198459A1
• Filed: 01/05/2018
• Published: 07/12/2018
• Est. Priority Date: 01/11/2017
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Inventors: Enright, Peter, Mincica, Martina, Downey, Fergus
• Granted Patent: US 10,200,055 B2
• Time in Patent Office: Days
• CPC Class Codes: H03M 1/0863 of switching transients, e.g. glitches
• CPC Class Codes: H03M 1/1009 Calibration
• CPC Class Codes: H03M 1/1038 by storing corrected or correction values in one or more digital look-up tables H03M1/1057 takes precedence
• CPC Class Codes: H03M 1/1057 by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/785 using resistors, i.e. R-2R ladders

Abstract

Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.

Claims

1. A method for characterizing transient behavior associated with a digital-to-analog converter (DAC) circuit, the method comprising:

generating a series of DAC circuit input events resulting in respective transients at an output of the DAC circuit;

using an integrator circuit, summing contributions from the respective transients to determine a DAC circuit output offset value representative of the transients.

2. The method of claim 1, wherein the generating the series of events includes generating such events at a specified repetition rate;

and

wherein the DAC circuit output offset value corresponds to the specified repetition rate.

3. The method of claim 2, comprising estimating a representative transient glitch area value using the output offset value.

4. The method of claim 2, wherein the series of events comprise a series of DAC circuit register writes.

5. The method of claim 4, wherein the DAC circuit register writes comprise a DAC circuit output update lacking an output level shift.

6. The method of claim 4, wherein the DAC circuit register writes comprise a DAC circuit output update including a direct-current (DC) value step-change in the DAC circuit output.

7. The method of claim 6, wherein the DAC circuit register writes comprise output updates including a first-polarity DC value step-change during a first period and a second, opposite-polarity DC value step-change during a second period.

8. The method of claim 7, comprising swapping an input polarity to the integrator circuit such that a first input polarity is used during the first period and a second, opposite input polarity is used during the second period.

9. The method of claim 1, wherein the series of events comprises a series of DAC circuit register writes including a first portion of register writes associated with DAC circuit output update commands and a second portion of register writes without associated DAC circuit output update commands;

and

wherein the method comprises removing a baseline contribution to the output offset value corresponding to the DAC circuit register writes without associated output update commands, to determine an output offset value corresponding to DAC circuit output update events.

10. The method of claim 1, comprising

wherein the integrator circuit is located within a commonly-shared integrated circuit comprising the DAC circuit;

and

wherein the method comprises comparing the output offset value representative of the transients to a specified threshold to determine an output offset value in terms of a count of least-significant bit (LSB) contributions; and

applying an offset compensation corresponding to the count.

11. The method of claim 10, wherein the offset compensation is applied using at least one fractional LSB contribution.

12. A digital-to-analog converter (DAC) circuit, comprising:

a digital input configured to trigger respective transients at an analog output;

an integrator circuit configured to sum contributions from the respective transients to determine a DAC circuit output offset value representative of the transients; and

an offset compensation circuit configured to apply an offset compensation to the analog output corresponding to the determined DAC circuit output offset value.

13. The DAC circuit of claim 12, wherein the integrator circuit comprises a capacitor;

and

wherein the offset compensation circuit comprises a comparator circuit including an input coupled to the capacitor, the comparator circuit arranged to compare the DAC circuit output offset value as represented by a voltage on the capacitor to a specified threshold to determine the output offset value; and

wherein the DAC circuit is configured to apply the offset compensation in response to an output of the comparator circuit.

14. The DAC circuit of claim 13, wherein an output circuit configuration of the DAC circuit comprises a redundant architecture;

and

wherein the DAC circuit is configured to apply offset compensation using an output contribution provided by a redundant element in the redundant architecture.

15. The DAC circuit of claim 14, wherein the redundant element comprises a fractional LSB contribution.

16. The DAC circuit of claim 12, wherein the generating the events or receiving the series of events includes generating or receiving such events at a specified repetition rate;

and

wherein the DAC circuit output offset value corresponds to the specified repetition rate.

17. The DAC circuit of claim 13, wherein the series of events comprise a series of DAC circuit register writes.

18. The DAC circuit of claim 13, wherein the DAC circuit register writes comprise output updates including a first-polarity DC value step-change during a first period and a second, opposite-polarity DC value step-change during a second period.

19. The DAC circuit of claim 13, comprising a switching circuit to swap an input polarity to the integrator circuit such that a first input polarity is used during the first period and a second, opposite input polarity is used during the second period.

20. An apparatus for characterizing transient behavior associated with a digital-to-analog converter (DAC) circuit, the apparatus including:

a means for generating a series of DAC circuit input events resulting in respective transients at an output of the DAC circuit;

and a means for summing contributions from the respective transients to determine a DAC circuit output offset value representative of the transients;

wherein the means for generating the series of events is configured to generate such events at a specified repetition rate; and

wherein the DAC circuit output offset value corresponds to the specified repetition rate.