TIME AND FREQUENCY DOMAIN BASED STEP COUNTER

• US 20180203032A1
• Filed: 05/27/2015
• Published: 07/19/2018
• Est. Priority Date: 04/29/2014
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Gaddam, Vasanth, Zhang, Yifeng, Zhang, Jie, Wu, Yuanwei, Wang, Guanqing
• Granted Patent: US 10,119,986 B2
• Time in Patent Office: Days
• CPC Class Codes: A61B 5/1118 Determining activity level
• CPC Class Codes: A61B 5/1123 Discriminating type of movement, e.g. walking or running A61B5/1116, A61B5/112 take precedence
• CPC Class Codes: A61B 5/725 using specific filters therefor, e.g. Kalman or adaptive filters A61B5/316 take precedence
• CPC Class Codes: A61B 5/7264 Classification of physiological signals or data, e.g. using neural networks, statistical classifiers, expert systems or fuzzy systems neural networks per se G06N3/00; expert systems per se G06N5/00
• CPC Class Codes: G01C 21/20 Instruments for performing navigational calculations G01C21/24, G01C21/26 take precedence
• CPC Class Codes: G01C 22/006 Pedometers
• CPC Class Codes: G01P 15/00 Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
• CPC Class Codes: G16H 50/20 for computer-aided diagnosis, e.g. based on medical expert systems
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A system for counting steps comprising a 3-D accelerometer is disclosed. The system also includes a pre-processor module coupled to the 3-D accelerometer and a dominant component computation unit coupled to the pre-processor module. The dominant component computation unit is configured to identify a dominant component in an output of the 3-D accelerometer. The system further includes a step counter for counting a number of steps using the output of the dominant component computation unit. The step counter includes a Fast Fourier Transform (FFT) module and a direct current (DC) remover module to remove a static component from the output of the FFT module. The step counter also includes a derivative filter and a zero crossing detector.

Claims

1. A system for counting steps, the system comprising:

a three-dimensional (3-D) accelerometer sensor-circuitry including sensor circuits configured and arranged to generate and output accelerometer data associated with three perpendicular axes;

pre-processor circuitry coupled to the 3-D accelerometer sensor-circuitry configured and arranged to produce filtered accelerometer data;

dominant component computation circuitry coupled to the pre-processor circuit, wherein the dominant component computation circuit is configured and arranged to identify a dominant component among vertical and horizontal component data in the output of the 3-D accelerometer sensor-circuitry; and

step counter circuitry configured and arranged to count a number of steps using the output of the dominant component computation circuit, wherein the step counter circuit includes a Fast Fourier Transform (FFT) circuit and a direct current (DC) remover circuit configured and arranged to remove a static component from an output of the FFT circuit, an activity frequency selector circuit a derivative filter circuit and a zero crossing detector circuit.

2. The system of claim 1, further comprising a statistics generator module, including circuitry, coupled to the dominant component computation circuitry and the pre-processor circuitry.

3. The system of claim 2, further comprising a classifier, including circuitry, configured and arranged to determine an activity based on outputs of the dominant component computation circuitry and the statistics generator module.

4. The system of claim 3, wherein the step counter circuitry is configured to refine an output of the step counter circuitry based on an output of the classifier.

5. The system of claim 1, further including post-processor circuitry that is configured to refine an output of the step counter circuitry.

6. The system of claim 2, wherein the statistics generator module includes a first statistics circuit and a second statistics circuit, wherein the first statistics circuit is configured to generate statistics and frequency domain transformation based on an output of the dominant component computation circuitry and the second statistics circuit is configured to generate statistics and frequency domain transformation based on an output of the pre-processor circuitry.

7. The system of claim 1, wherein the pre-processor circuitry is configured to remove at least one of a direct current (DC) component in a vector sample received from the 3-D accelerometer sensor-circuitry and a high frequency component from the vector sample.

8. The system of claim 7, wherein the dominant component computation circuitry is configured to determine a dominant component in the vector sample.

9. The system of claim 8, wherein the vector sample includes the horizontal component data and the vertical component data.

10. The system of claim 9, wherein the vertical component data is proportional to a vector inner product between a mean vector of a plurality of vector samples along three axes and each dynamic vector corresponding to a first difference between each of the plurality of vector samples and the mean vector.

11. The system of claim 10, wherein the horizontal component data is related to a norm of a second difference between the first difference and the mean vector scaled by the vertical component data.

12. The system of claim 1, wherein the pre-processor circuitry includes at least one of a level normalization circuit, a DC notch filter circuit and a low pass filter circuit.

13. The system of claim 1, further including an activity classifier circuit, wherein the activity classifier circuit is configured and arranged to refine an output of the step counter circuitry.

14. The system of claim 13, wherein the activity classifier circuit is embodied in an external device that is configured and arranged to communicate with the step counter circuitry.

15. A non-transitory computer readable media including programming instruction which when executed by a processor performs an operation of counting steps, the operation includes:

receiving an output from three-dimensional (3-D) accelerometer sensor-circuitry, including sensor circuits, configured and arranged to generate and output accelerometer data associated with three perpendicular axes;

pre-processing the received output of the 3-D accelerometer sensor-circuitry, wherein the pre-processing includes removing a direct current (DC) component from the output of the 3-D accelerometer sensor-circuitry;

determining a dominant component among vertical component data and horizontal component data in the output of the 3-D accelerometer sensor-circuitry after the pre-processing, wherein the output of the 3-D accelerometer sensor-circuitry is used to derive the vertical component data and the horizontal component data, the vertical component data is proportional to a vector inner product between a mean vector of a plurality of vector samples along the three perpendicular axes and each dynamic vector corresponding to a first difference between each of the plurality of vector samples and the mean vector, wherein the horizontal component data is related to a norm of a second difference between the first difference and the mean vector scaled by the vertical component data; and

counting steps using the dominant component, wherein the counting includes performing a Fast Fourier Transform (FFT) and zero crossing detection.

16. The computer readable media of claim 15, further including programming instructions to collect statistical data based on at least one of a time domain data and frequency domain data derived from the accelerometer data or the dominant component, and determining an activity type.

17. The computer readable media of claim 16, wherein the counting is refined to remove false steps using the activity type.

18. The computer readable media of claim 15, wherein the operation further includes removing a high frequency component from the vector sample.

19. The computer readable media of claim 15, wherein determining the dominant component includes determining in a vector sample in the plurality of vector samples, wherein the vector sample includes the horizontal component data and the vertical component.

20. The computer readable media of claim 19, wherein the vertical component data is proportional to a vector inner product between a mean vector of a plurality of vector samples along three axes and each dynamic vector corresponding to a first difference between each of the plurality of vector samples and the mean vector.