CO-PACKAGING PHOTONIC INTEGRATED CIRCUITS AND APPLICATION SPECIFIC INTEGRATED CIRCUITS

• US 20180203187A1
• Filed: 01/12/2018
• Published: 07/19/2018
• Est. Priority Date: 04/26/2012
• Status: Active Grant

• Current Assignee: Acacia Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Acacia Communications Incorporated (Cisco Systems, Inc.)
• Inventors: Doerr, Christopher, Swanson, Eric, Vermeulen, Diedrik, Azemati, Saeid, Stahl, Jon
• Granted Patent: US 10,578,799 B2
• Time in Patent Office: Days
• CPC Class Codes: G02B 6/12 of the integrated circuit kind electric integrated circuits H01L27/00
• CPC Class Codes: G02B 6/4269 with heat sinks or radiation fins
• CPC Class Codes: G02B 6/428 containing printed circuit boards [PCB]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

Disclosed herein are designs, structures and techniques for advanced packaging of multi-function photonic integrated circuits that allow such high-performance multi-function photonic integrated circuits to be co-packaged with a high-performance multi-function ASIC thereby significantly reducing strenuous interconnect challenges and lowering costs, power and size of the overall devices.

Claims

1. An co-packaging arrangement for a photonic integrated circuit (PIC) and an application specific integrated circuit (ASIC) comprising:

the PIC and the ASIC positioned within a single shared housing;

wherein said PIC includes at least two optical fibers that couple light between structures outside the housing to optical waveguides on the PIC, wherein said PIC includes optical modulators and optical detectors and said shared housing includes electrical interconnects for interconnecting the PIC to the ASIC.

2. The arrangement according to claim 1 wherein a said PIC includes at least two surface grating couplers.

3. The arrangement according to claim 1 wherein a transimpedance amplifier (TIA) for the PIC is located on the ASIC with no active electrical elements in-between the PIC and the ASIC.

4. The arrangement according to claim 1 wherein a PIC optical modulator is driven directly from a digital-to-analog converter (DAC) that is located on the ASIC.

5. The arrangement according to claim 1 wherein the ASIC includes a driver amplifier and a transimpedance amplifier (TIA) for the PIC and there is no active electrical elements connecting the PIC and the ASIC.

6. The arrangement of claim 1 wherein a master laser is housed outside of the housing and there are at least three optical fibers coupling laser light, received input signal light, and modulated transmitter output light respectively with the PIC, and there are no cooling devices within the housing.

7. The arrangement of claim 1 wherein the PIC includes a number of high-speed Input/Output connectors positioned along one single edge of the PIC.

8. The arrangement of claim 1 further including a common substrate having active electrical elements which interconnect the PIC and the ASIC.

9. The arrangement of claim 1 wherein the housing includes a heat sink overlying a top of the housing, wherein said housing includes an opening through which the optical fibers pass.

10. The arrangement of claim 1 wherein the housing includes a window through which light is coupled to the PIC to/from fibers via the window and one or more lense(s).

11. The arrangement of claim 1 wherein the PIC is mounted on a PIC wrap-around-carrier having contact pads such that the PIC is mounted at an angle relative to the surface of the ASIC.

12. The arrangement of claim 1 wherein the ASIC is flip-chip mounted and die bonded to a common substrate bonded to the PIC, said substrate having ball bonds to bond to a circuit board external to the housing.