NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

• US 20180203796A1
• Filed: 11/15/2017
• Published: 07/19/2018
• Est. Priority Date: 01/18/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, JI-YOON, PARK, Hyun-Wook
• Granted Patent: US 10,268,575 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/562 Multilevel memory programming aspects
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/563 Multilevel memory reading aspects
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile memory device includes control logic and a memory cell array. The memory cell array includes a first plane and a second plane. The control logic is configured to perform a first sub-operation on the first plane, to perform a second sub-operation on the second plane, to delay the second sub-operation as much as a reference time so that a partial section of the first sub-operation does not overlap the second sub-operation, and to variably control the reference time.

Claims

1. A nonvolatile memory device comprising:

a memory cell array including a first plane and a second plane; and

a control logic circuit configured to execute a first sub-operation on the first plane, and to execute a second sub-operation on the second plane,

wherein the control logic circuit is further configured to control a delay of an execution of the second sub-operation according to a reference time so that execution of a particular section of the first sub-operation does not overlap execution of the second sub-operation, and the control logic circuit is configured to vary the reference time to increase or decrease the delay of the execution of the second sub-operation,

wherein the particular section of the first sub-operation indicates a noise section where a power noise occurs, and

wherein the second sub-operation indicates an operation of a victim section affected by the power noise.

2. The nonvolatile memory device of claim 1, further comprising:

an address decoder connected to the memory cell array through a plurality of word lines, and configured to selectively provide word line voltages to at least one of the plurality of word lines; and

a voltage generator configured to generate voltages, which are provided to the address decoder in response to receiving a control signal from the control logic circuit, wherein the voltage generator generates the word line voltages including at least one of a program voltage, a pass voltage, and a program verification voltage.

3. The nonvolatile memory device of claim 1, wherein the first sub-operation indicates a bit line precharge operation of a read operation on the first plane, and

wherein the second sub-operation indicates a bit line sensing operation of a read operation on the second plane.

4. The nonvolatile memory device of claim 1, wherein the control logic circuit is configured to increase the reference time as a level of a read voltage in a read operation performed on the first plane increases.

5. The nonvolatile memory device of claim 4, wherein the reference time includes a first reference time and a second reference time, and

when the read operation is executed on the first plane using one of a plurality of first read voltages included in a first read voltage group, the control logic circuit is configured to delay the second sub-operation based on the first reference time,

wherein when the read operation is performed on the first plane using one of a plurality of second read voltages included in a second read voltage group, the control logic circuit is configured to delay the second sub operation based on the second reference time, wherein the second reference time is greater than the first reference time, and

wherein the second read voltages are higher than the first read voltages.

6. The nonvolatile memory device of claim 1, wherein the first sub-operation indicates a bit line setup operation of a program operation on the first plane, and

wherein the second sub-operation indicates a bit line sensing operation of a program operation on the second plane.

7. The nonvolatile memory device of claim 1, wherein the control logic circuit is configured to increase the reference time when a program loop increases in a program operation on the first plane.

8. The nonvolatile memory device of claim 7, wherein the program loop includes a first program loop and a second program loop, and the reference time includes a first reference time and a second reference time,

when the first program loop is performed on the first plane, the control logic circuit is configured to delay the second sub-operation based on the first reference time, and

wherein when the second program loop is performed on the second plane, the control logic circuit is configured to delay the second sub-operation based on the second reference time, wherein the second reference time is greater than the first reference time.

9. The nonvolatile memory device of claim 1, wherein the first plane includes first memory blocks which share first bit lines, and

wherein the second plane includes second memory blocks that share second bit lines.

10. The nonvolatile memory device of claim 1, wherein the control logic circuit comprises:

a register circuit configured to store information about the reference time;

a first plane control circuit configured to store a first command and to control the first sub-operation based on the first command and the information about the reference time; and

a second plane control circuit configured to store a second command and to control the second sub-operation based on the second command and the information about the reference time.

11. The nonvolatile memory device of claim 1, wherein the reference time is set based on the particular section of the first sub-operation wherein a magnitude of the power noise is greater than a reference power.

12. The nonvolatile memory device of claim 1, wherein when execution of the second sub-operation is performed prior to execution of the first sub-operation, the control logic circuit is configured to perform the first sub-operation after the second sub-operation is completed.

13. A memory system comprising:

a nonvolatile memory device configured to include a first area and a second area, to execute a first sub-operation on the first area, to execute a second sub-operation on the second area, and to delay execution of the second sub-operation according to a reference time so that execution of a particular section of the first sub-operation does not overlap execution of the second sub-operation; and

a memory controller configured to vary the reference time to increase or decrease the delay of execution of the second sub-operation.

14. The memory system of claim 13, wherein each of the first area and the second area is constituted in units of a memory chip.

15. The memory system of claim 13, wherein the reference time comprises a first reference time and a second reference time, and

when a read operation is performed on the first area using a first read voltage, the second sub-operation is delayed based on the first reference time, and

wherein when the read operation is performed on the first area using a second read voltage higher than the first read voltage, the second sub-operation is delayed based in the second reference time, wherein the second reference time is greater than the first reference time.

16. The memory system of claim 13, wherein the reference time comprises a first reference time and a second reference time, and

when a first program loop is executed on the first area, the execution of the second sub-operation is delayed based on the first reference time, and

wherein when a second program loop is performed on the first area, the second sub-operation is delayed based on the second reference time, wherein the second reference time is longer than the first reference time.

17. A solid state drive (SSD), comprising:

a plurality of memory chips;

an SSD controller configured to;

control execution of a program operation performed by the plurality of memory chips;

determine when operation of a noise section of at least one memory chip from among the memory chips overlaps operation of a victim section of another memory chip from among the plurality of memory chips; and

delay execution of the operation of the victim section of the another memory chip based on a reference time.

18. The SSD according to claim 17, wherein the plurality of memory chips comprise nonvolatile memory chips.

19. The SSD according to claim 17, further comprising a signal connector that receives a signal from a host, and a power connector that receives power from an external source;

and

wherein the reference time comprises a suspend time (SPD_T), and a buffer configured to store a mapping table including a suspend time table of the memory chips.

20. The SSD according to claim 19, wherein the SSD controller is configured to vary the reference time.