Three-Dimensional Vertical One-Time-Programmable Memory Comprising Multiple Antifuse Sub-Layers
First Claim
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1. 1A three-dimensional vertical one-time-programmable memory (3D-OTPV), comprising:
- a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit;
a plurality of memory holes through said horizontal address lines;
an antifuse layer on the sidewalls of said memory holes, said antifuse layer comprising at least first and second sub-layers, wherein said first and second sub-layers comprise different antifuse materials;
a plurality of vertical address lines in said memory holes;
a plurality of OTP cells at the intersections of said horizontal address lines and said vertical address lines.
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Abstract
The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises horizontal address lines and memory holes there-through, an antifuse layer and vertical address lines in said memory holes. The antifuse layer comprises at least first and second sub-layers with different antifuse materials. The 3D-OTPV comprises no separate diode layer.
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Citations
11 Claims
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1. 1A three-dimensional vertical one-time-programmable memory (3D-OTPV), comprising:
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a semiconductor substrate comprising a substrate circuit; a plurality of vertically stacked horizontal address lines above said semiconductor circuit; a plurality of memory holes through said horizontal address lines; an antifuse layer on the sidewalls of said memory holes, said antifuse layer comprising at least first and second sub-layers, wherein said first and second sub-layers comprise different antifuse materials; a plurality of vertical address lines in said memory holes; a plurality of OTP cells at the intersections of said horizontal address lines and said vertical address lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification