ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

• US 20180211984A1
• Filed: 01/18/2017
• Published: 07/26/2018
• Est. Priority Date: 08/31/2016
• Status: Abandoned Application

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Zeng, Mian
• Application Number:
  US15/500,125
• Publication Number:
  US 20180211984A1
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H05K 2203/0384 : Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
• CPC Class Codes: H10K 10/462 : Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/482 : the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 10/484 : characterised by the channel regions
• CPC Class Codes: H10K 10/486 : the channel region comprising two or more active layers, e.g. forming pn heterojunctions
• CPC Class Codes: H10K 10/84 : Ohmic electrodes, e.g. source or drain electrodes

Abstract

Disclosed are an array substrate and a method for manufacturing the same. The array substrate includes a transmission gate structure having an upper thin film transistor and a lower thin film transistor. An active layer of the lower TFT is the first active layer, and an active layer of the upper TFT is the second active layer. The first active layer and the second active layer are provided on two sides of a source and drain layer, respectively, and share source and drain electrodes. Compared with the prior art, such structure is simpler, and furthermore it facilitates simplification of a manufacturing process of the transmission gate structure and improves a success rate of preparation thereof.

Claims

1. An array substrate, comprising a transmission gate structure which comprises from bottom to top:

a first gate provided on a substrate;

a first gate insulating layer provided on the first gate and completely covering the first gate;

a first active layer provided on the first gate insulating layer and opposite to the first gate;

an insulating layer provided on the first active layer;

a source and drain layer, provided on the insulating layer and electrically connected to the first active layer by means of a via hole located on the insulating layer;

a second active layer provided on the source and drain layer;

a second gate insulating layer provided on the second active layer and completely covering the second active layer; and

a second gate provided on the second gate insulating layer and opposite to the second active layer.

2. The array substrate according to claim 1, wherein the first active layer is an N-type active layer and the second active layer is a P-type active layer.

3. The array substrate according to claim 1, wherein the insulating layer comprises an etch stop layer and/or a planarization layer.

4. The array substrate according to claim 3, wherein when the insulating layer comprises an etch stop layer and a planarization layer, the etch stop layer being provided on the first active layer, and the planarization layer being provided on the etch stop layer.

5. The array substrate according to claim 3, wherein the etch stop layer is made of a silicon nitride and/or a silicon oxide.

6. A method for manufacturing an array substrate, wherein the method comprises following steps of:

step S1, obtaining a substrate;

step S2, forming a first gate on the substrate;

step S3, forming a first gate insulating layer completely covering the first gate on the first gate;

step S4, forming a first active layer on the first gate insulating layer, the first active layer being opposite to the first gate;

step S5, forming an insulating layer on the first active layer and patterning the insulating layer to form a via hole;

step S6, forming a source and drain layer on the insulating layer, the source and drain layer being electrically connected to the first active layer by means of the via hole;

step S7, forming a second active layer on the source and drain layer;

step S8, forming a second gate insulating layer completely covering the second active layer on the second active layer; and

step S9, forming a second gate opposite to the second active layer on the second gate insulating layer.

7. The method according to claim 6, wherein the first active layer is an N-type active layer and the second active layer is a P-type active layer;

and

wherein the first active layer is made of a metal oxide material, and the second active layer is made of a P-type organic semiconductor material.

8. The method according to claim 6, the insulating layer comprises an etch stop layer and/or a planarization layer.

9. The method according to claim 8, wherein when the insulating layer comprises an etch stop layer and a planarization layer, the step S5 comprises:

step S51, forming an etch stop layer covering the first active layer on the first active layer;

step S52, forming a planarization layer covering the etch stop layer on the etch stop layer; and

step S53, patterning the etch stop layer and the planarization layer to form a via hole penetrating both the planarization layer and the etch stop layer.

10. The method according to claim 8, wherein the etch stop layer is made of a silicon nitride and/or a silicon oxide.