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Configurable Computing Array Based on Three-Dimensional Printed Memory

  • US 20180212606A1
  • Filed: 03/19/2018
  • Published: 07/26/2018
  • Est. Priority Date: 03/05/2016
  • Status: Active Grant
First Claim
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1. A configurable computing element, comprising:

  • a semiconductor substrate including transistors thereon;

    at least first and second three-dimensional printed memory (3D-P) arrays stacked above said semiconductor substrate, wherein said first 3D-P array stores at least a first portion of a first look-up table (LUT) for a first basic function, and said second 3D-P array stores at least a second portion of a second LUT for a second basic function;

    at least an internal configurable interconnect coupling with said first and second 3D-P arrays, wherein said configurable computing element selectively realizes said first or second basic function depending upon at least a configuration signal on said internal configurable interconnect.

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